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freescale semiconductor data sheet: technical data document number: PXD10 rev. 1, 09/2011 PXD10 416 tepbga 27 mm x 27 mm 176 lqfp 24 mm x 24 mm 208 lqfp 28 mm x 28 mm ? freescale semiconductor, inc., 2011. all rights reserved. the PXD10 family represents a new generation of 32-bit microcontrollers based on the power architecture ? . these devices provide a cost-effective, single chip display solution for the industrial market. an integrated tft driver with digital video input ability from an external video source, significant on-chip memory, and low power design methodologies provide flexibility and reliability in meeting di splay demands in rugged environments. the advanced processor core offers high performance processing optimized for low power consumption, operating at speeds as high as 64 mhz. the family itself is fully scalable from 512 kb to 1 mb internal flash memory. the memory capacity can be further expanded via the on-chip quadspi serial fl ash controller module. the PXD10 family platform has a single level of memory hierarchy supporting on-chip sram and flash memories. the 1 mb flash version features 160 kb of on-chip graphics sram to buffer cost effective color tft displays driven via the on-chip display control unit (dcu). see table 1 for specific memory size and feat ure sets of the product family members. the PXD10 family benefits from the extensive development infrastructure for power architecture devices, which is alrea dy well established. this includes full support from available software drivers, operating systems, and configuration code to assist with users? implementations. see section 3, developer support, for more information. PXD10 microcontroller data sheet 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 PXD10 series blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 PXD10 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6 details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pinout and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 27 2.1 144 lqfp package pinouts . . . . . . . . . . . . . . . . . . . . . 27 2.2 176 lqfp package pinout . . . . . . . . . . . . . . . . . . . . . . 29 2.3 pad configuration during reset phases . . . . . . . . . . . . . 30 2.4 voltage supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.5 pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.6 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.7 debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8 port pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 57 3.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62 3.6 electromagnetic compatibility (emc) characteristics . . 65 3.7 power management electrical characteristics . . . . . . . 67 3.8 i/o pad electrical characteristics . . . . . . . . . . . . . . . . . 75 3.9 ssd specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.10 reset electrical characteristics . . . . . . . . . . . . . . . . . 84 3.11 fast external crystal oscillator (4?16 mhz) electrical characteristics87 3.12 slow external crystal oscillator (32 khz) electrical characteristics89 3.13 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 91 3.14 fast internal rc oscillator (16 mhz) electrical characteristics 92 3.15 slow internal rc oscillator (128 khz) electrical characteristics92 3.16 flash memory electrical characteristics . . . . . . . . . . . . 93 3.17 adc electrical characteristics. . . . . . . . . . . . . . . . . . . . 94 3.18 lcd driver electrical characteristics . . . . . . . . . . . . . . 101 3.19 pad ac specifications. . . . . . . . . . . . . . . . . . . . . . . . . 102 3.20 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.1 144 lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.2 176 lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 2 1 overview 1.1 document overview this document describes the device features and highlights important electrical and physical characteristics. for functi onal characteristics, see the PXD10 microcontroller reference manual. 1.2 description the PXD10 family of chips is designed to enable the development of industr ial hmi applications by providing a single-chip solution capable of hosting re al-time applications and driving a tft display directly using an on-chip co lor tft display controller. PXD10 chips incorporate a cost-efficient host pro cessor core compliant with the power architecture ? embedded category. the processor is 100% user-mode compatible with the power architecture and capitalizes on the available development infrastruct ure of current power archi tecture devices with full support from available software driver s, operating systems and configurati on code to assist with users' implementations. offering high performance processing at speeds up to 64 mhz, the PXD10 family is optimized for low power consumption and supports a ra nge of on-chip sram and internal flash memory sizes. the version with 1 mb of flash memory (PXD1010) feat ures 160 kb of on-chip graphics sram. see table 1 for specific memory a nd feature sets of the product family members. 1.3 device comparison table 1. PXD10 family feature set feature PXD1005 PXD1010 cpu e200z0h execution speed static ? 64 mhz flash (ecc) 512 kb 1 mb eeprom emulation block (ecc) 4 16 kb ram (ecc) 48 kb graphics ram no 160 kb mpu 12 entry edma 16 channels display control unit (dcu) no yes parallel data interface no yes stepper motor controller (smc) 6 motors stepper stall detect (ssd) yes sound generation logic (sgl) yes
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 3 lcd driver 64 6 40 4, 38 6 32 khz slow external crystal oscillator yes real-time counter and autonomous periodic interrupt ye s periodic interrupt timer (pit) 4 ch, 32-bit software watchdog timer (swt) yes system timer module (stm) 4 ch, 32-bit timed i/o (emios) 8 ch, 16-bit ic/oc 16 ch, 16-bit pwm/ic/oc adc 16 channels, 10-bit can (64 mailboxes) 2 can can sampler yes sci 2 uart spi 2 spi 3 spi quadspi serial flash interface no yes i 2 c24 gpio 105 105 (144-pin package) 133 (176-pin package) debug nexus 1 nexus 2+ package 144 lqfp 144 lqfp 176 lqfp table 1. PXD10 family feature set (continued) feature PXD1005 PXD1010
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 4 1.4 PXD10 series blocks 1.4.1 block diagram figure 1 shows a high-level block di agram of the PXD10 series. figure 1. PXD10 series block diagram crossbar switch (xbar) PXD10 block diagram integer multiply e200z0 core unit execution unit instruction unit vle general load/store unit purpose registers (32 x 32-bit) branch unit intc jtag peripheral i/o bridge (pbridge) oscillators bam rtc pll pit swt aux pll vreg stm data bus instruction bus memory protection unit (mpu) uart/lin adc lcd seg spi i 2 c emios can siu smd ssd ram controller quadspi eeprom (emulation) flash (ecc) ram controller flash controller flash (ecc) graphics sram sram (ecc) nexus2+ display control unit (tfts) edma adc ? analog-to-digital converter bam ? boot assist module can ? controller area network controller ecc ? error correction code edma ? enhanced direct memory access controller emios ? timed input/output i 2 c ? inter-integrated circuit controller intc ? interrupt controller jtag ? joint test action group interface lcd ? liquid crystal display pit ? periodic interrupt timer pll ? phase-locked loop rtc ? real time clock siu ? system integration unit smd ssd ? stepper motor driver/stepper stall detect spi ? serial peripheral interface controller sram ? static random-access memory stm ? system timer module swt ? software watchdog timer uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network vle ? variable-length execution set vreg ? voltage regulator
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 5 1.5 PXD10 features 1.5.1 summary ? single issue, 32-bit power architecture t echnology compliant cpu core complex (e200z0h) ? compatible with power architecture instruction set ? includes variable length encoding (vle) instruction set for smalle r code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possibl e to achieve significant code size footprint reduction over conventional book e compliant code ? on-chip ecc flash memory with flash controller ? as much as 1 mb primary flas h?two 512 kb modules with pref etch buffer and 128-bit data access port ? 64 kb data flash?separate 4 ? 16 kb flash block for eeprom em ulation with prefetch buffer and 128-bit data access port ? as much as 48 kb on-chip ecc sram with sram controller ? as much as 160 kb on-chip non-ecc gr aphics sram with sram controller ? memory protection unit (mpu) with as many as 12 region descriptors and 32-byte region granularity to provide basi c memory access permission ? interrupt controller (intc) wi th as many as 127 peripheral interr upt sources and eight software interrupts ? two frequency-modulated ph ase-locked loops (fmplls) ? primary fmpll provides a 64 mhz system clock ? auxiliary fmpll is available for use as an alternate, modulated or non-modulated clock source to emios modules and as alternate cl ock to the dcu for pixel clock generation ? crossbar switch architecture enables concurrent access of peripherals, flash memory or ram from multiple bus masters (amba 2.0 v6 ahb) ? 16-channel enhanced direct memory access cont roller (edma) with multiple transfer request sources using a dma channel multiplexer ? boot assist module (bam) supports internal fl ash programming via a se rial link (flexcan or linflex) ? display control unit to drive tft lcd displays ? includes processing of as many as four planes that can be blended together ? offers a direct unbuffered hardwa re bit-blitter of as many as 16 software -configurable dynamic layers in order to drastically minimize gr aphic memory requireme nts and provide fast animations ? programmable display resoluti ons are available up to wvga ? parallel data interface (p di) for digital video input ? lcd segment driver module with two software programmable configurations: ? as many as 40 frontplane driver s and four backplane drivers
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 6 ? as many as 38 frontplane drivers and six backplane drivers ? stepper motor controller (smc) module with high-current driver s for as many as six stepper motors driven in full dual h-bridge configurat ion including full diagnostics for short circuit detection ? stepper motor return-to-zero and stall detection module ? sound generation and playback utilizing pwm channels and edma; supports monotonic and polyphonic sound ? 24 emios channels providing as many as 16 pwm and 24 input capture / output compare channels ? 10-bit analog-to-digital converter (adc) ? maximum conversion time of 1 s ? as many as 16 internal channels, expa ndable to 23 via external multiplexing ? as many as two serial peripheral interface (dspi) modules for full-duplex, synchronous, communications with external devices (extendable to include up to 8 multiplexed external channels) ? quadspi serial flash memory controller suppor ting single, dual and quad modes of operation to interface to external serial flash memory. quadspi can be configured to function as another dspi module. ? two local interconnect network flexible (lin flex) controller modules capable of autonomous message handling (master), autonomous header handling (slave mode), and uart support. compliant with lin protocol rev 2.1 ? two full can 2.0b controllers with 64 configurable buffers each; bi t rate programmable as fast as 1 mbit/s ? as many as four inter- integrated circuit (i 2 c) internal bus controller s with master/slave bus interface ? as many as 133 configurable general purpose pins supporting input and output operations ? real time counter (rtc) w ith multiple clock sources: ? 128 khz slow internal rc os cillator or 16 mhz fast inte rnal rc oscillator supporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds ? 32 khz slow external crysta l oscillator, supporting wakeup wi th 1 s resolution and maximum timeout of one hour ? 4?16 mhz fast external crystal oscillator ? system timers: ? four-channel 32-bit system timer module (stm)?included in processor platform ? four-channel 32-bit periodic interrupt timer (pit) module ? software watchdog timer (swt) ? system integration unit (siu) module to manage re sets, external interrupts, gpio and pad control ? system status and configuration module (sscm) to provide inform ation for identification of the device, last boot mode, or debug status and provi des an entry point for the censorship password mechanism
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 7 ? clock generation module (mc_cgm) to generate system clock sources and provide a unified register interface, enabling access to all clock sources ? clock monitor unit (cmu) to monitor the integrit y of the main crystal oscillator and the pll and act as a frequency meter, meas uring the frequency of one clock source and comparing it to a reference clock ? mode entry module (mc_me) to control the de vice power mode, i.e., run, halt, stop, or standby, control mode transition sequences, and manage the power control, voltage regulator, clock generation and cl ock management modules ? reset generation module (mc_rgm) to manage rese t assertion and release to the device at initial power-up ? nexus development interf ace (ndi) per ieee-isto 5001- 2003 class two plus standard ? device/board boundary-sca n testing supported per joint test action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator contro ller for regulating the 3.3 or 5 v supply voltage down to 1.2 v for core logic (requires exte rnal ballast transistor) ? the PXD10 microcontrollers are of fered in the following packages: 1 ? 144 lqfp, 0.5 mm pitch, 20 mm ? 20 mm outline ? 176 lqfp, 0.5 mm pitch, 24 mm ? 24 mm outline 1.6 details 1.6.1 low-power operation PXD10 devices are designed for opt imized low-power operation and dynam ic power management of the core processor and peripherals. powe r management features include so ftware-controlled clock gating of peripherals and multiple power domains to minimize leakage in low-power modes. there are two static low-power modes, standby and stop, and two dynamic power modes?run and halt. both low power modes use clock gating to halt the clock for all or part of the device. the standby mode also uses power gatin g to automatically turn off the pow er supply to parts of the device to minimize leakage. standby mode turns off the power to the majority of the chip to offer the lowest power consumption mode. the contents of the cores, on-chip peripheral re gisters and potentially some of the volatile memory are lost. standby mode is configurable to make cert ain features available with the disadvantage that these consume additional current: ? it is possible to retain the contents of the full ram or only 8 kb. ? it is possible to enable the internal 16 mhz or 128 khz rc oscillator, the external 4?16 mhz oscillator, or the external 32 khz oscillator. ? it is possible to keep the lcd module active. 1. see the device comparison table or orderable parts summary for package offerings for each device in the family.
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 8 the device can be awakened from standby mode vi a from any of as many as 19 i/o pins, a reset or from a periodic wake-up usi ng a low power oscillator. stop mode maintains power to the entire device al lowing the retention of al l on-chip registers and memory, and providing a faster rec overy low power mode than the lo west standby mode. there is no need to reconfigure the de vice before executing code. the clocks to the core and peripherals are halted and can be optionally stopped to the oscillator or pll at the expense of a slower start-up time. stop is entered from run mode onl y. wake-up from stop mode is tr iggered by an external event or by the internal periodic wake-up, if enabled. run modes are the main operating mode where the enti re device can be powered and clocked and from which most processing activity is done. four dynamic run modes are s upported?run0 - run3. the ability to configure and se lect different run modes en ables different clocks and power configurations to be supported with respect to each other and to allow switching between different operating conditions. the necessary peripherals, clock sources , clock speed and system clock prescalers can be independently configured for each of the f our run modes of the device. halt mode is a reduced activity, low power mode intended for modera te periods of lower processing activity. in this mode the core sy stem clocks are stopped but user-selec ted peripheral tasks can continue to run. it can be configured to provi de more efficient power management features (switch-off pll, flash memory, main regulator, etc.) at the cost of longer wake up latency. the system returns to run mode as soon as an event or interrupt is pending.
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 9 table 1 summarizes the operating modes of PXD10 devices. table 1. operating mode summary 1 notes: 1 table key: on?powered and clocked op?optionally configurable to be enabled or disabled (clock gated) cg?clock gated, powered but clock stopped off?powered off and clock gated fp?vreg full performance mode lp?vreg low power mode, reduced output capability of vreg but lower power consumption var?variable duration, based on the required reconfiguration and execution clock speed bam?boot assist module software and hardware used for device start-up and configuration operating modes soc features clock sources periodic wake-up wake-up input vreg mode wake-up time 2 2 a high level summary of some key durations that need to be cons idered when recovering from low power modes. this does not accou nt for all durations at wake up. other delays will be necessary to consider incl uding, but not limited to the external supply start-up time. irc wake-up time must not be added to the overall wake-u p time as it starts in parallel with the vreg. all other wake-up times must be added to determine the total start-up time core peripherals flash ram graphics ram main pll auxiliary pll 16 mhz irc x osc 128 khz irc 32 khz x osc vreg start-up irc wake-up flash recovery osc stabilization pll lock s/w reconfig mode switch over run onopopononopoponoponop ? ? fp ? ? ? ? ? ? ? halt cg op op on on op op on op on op op op fp ? ? ? ? ? ? tbd stop cg cg cg on on cg cg op op on op op op lp 50 s 4 s 20 s 1ms 200 s ? 24 s standby off off 3 3 the lcd can optionally be kept running while the device is in standby mode. off cg 4 4 all of the ram contents is retained, but not accessible in standby mode. off off off op op on op op op lp 50 s 8 s 100 s 1ms 200 s var 28 s off off off 8k 5 5 8 kb of the ram contents is retained , but not accessible in standby mode. off off off op op on op op op lp 50 s 8 s 100 s 1ms 200 s var 28 s por 500 s 8 s 100 s 1ms 200 s bam
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 10 additional notes on low power operation: ? fast wake-up using the on-chip 16 mhz internal rc oscillator allows rapid execution from ram on exit from low power modes ? the 16 mhz internal rc oscillat or supports low speed code execut ion and clocking of peripherals when it is selected as the system clock and can also be used as the pll input clock source to provide fast start-up without th e external oscillator delay ? PXD10 devices include an intern al voltage regulator that includes the following features: ? regulates input to genera te all internal supplies ? manages power gating ? low power regulators support operation when in stop and standby modes to minimize power consumption ? startup on-chip regulators in <50 s for rapid exit of stop and standby modes ? low voltage detection on main supply and 1.2 v regulated supplies 1.6.2 e200z0h core processor the e200z0h processor is similar to other processors in the e200zx series but supports only the vle instruction set and does not include the signal processing extension for ds p applications or a floating point unit. the e200z0h has all the feat ures of the e200z0 plus: ? branch acceleration using br anch target buffer (btb) ? supports independent instruction and data accesse s to different memory subsystems, such as sram and flash memory via indepe ndent instruction and data bius the e200z0h processor uses a four stage in-order pipe line for instruction execution. the instruction fetch (stage 1), instruction decode/regis ter file read/effective address calculation (s tage 2), execute/memory access (stage 3), and regist er writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. the integer execution unit consists of a 32-bit arithmet ic unit (au), a logic unit (lu), a 32-bit barrel shifter (shifter), a mask-inserti on unit (miu), a condition regist er manipulation unit (cru), a count-leading-zeros unit (clz), an 8 32 hardware multip lier array, result feed-forward hardware, and a hardware divider. most arithmetic and logical operations are executed in a single cycl e with the exception of the divide and multiply instructions. a count-lead ing-zeros unit operates in a single clock cycle. the instruction unit contains a pc incrementer and a dedicated branch a ddress adder to minimize delays during change of flow operations. branch target prefet ching from the btb is performed to accelerate certain taken branches. sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. branch target prefetching is performed to accelerate taken branches. prefetched instructions are placed into an instruction buffer capable of holding four instructions. conditional branches not taken execute in a single clock. branches with su ccessful target prefetching have an effective execution time of one clock on e200z0h. all other taken branch es have an execution time of two clocks.
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 11 memory load and store operations are provided for byte, halfword, and word (32-bi t) data with automatic zero or sign extension of byte and halfword load da ta as well as optional byte reversal of data. these instructions can be pipelined to allow effective single cycle throughput. load and store multiple word instructions allow low overhead context save and restore operations. the load /store unit contains a dedicated effective address adder to allow effective addres s generation to be optimi zed. also, a load-to-use dependency does not incur any pipeline bubbles for most cases. the condition register unit supports the condition regi ster (cr) and condition re gister operations defined by the power architecture. the condition register consists of eight 4-bit fi elds that reflect the results of certain operations, such as move, integer and floati ng-point compare, arithmetic , and logical instructions, and provide a mechanism fo r testing and branching. vectored and autovectored interr upts are supported. hardware vectored interrupt support is provided to allow multiple interrupt sources to have unique in terrupt handlers invoked with no software overhead. the cpu includes support for variable length encoding (vle) instruction enhancements. this allows the classic powerpc instruction set to be represented by a modified instruct ion set made up fr om a mixture of 16-bit and 32-bit instructions. this re sults in a significantly smaller code size footprint without affecting performance noticeably. the cpu core is enhanced by an additional interrupt source?non mask able interrupt. this interrupt source is routed directly from package pins, via edge detection logic in the siu to the cpu, bypassing the interrupt controller completely. once the edge dete ction logic is programmed, it can not be disabled, except by reset. the non mask able interrupt is, as the name suggest s, completely un-maskable and when asserted will always result in th e immediate execution of the respective interrupt service routine. the non maskable interrupt is not guaranteed to be recoverable. the cpu core has an additional ?wait for interrupt? inst ruction that is used in conjunction with low power stop mode. when low power stop mode is selected, this instruction is executed to allow the system clock to be stopped. an external interr upt source or the system wake-up ti mer is used to re start the system clock and allow the cpu to service the interrupt. additional features include: ? load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles ? thirty-two 32-bit genera l purpose registers (gprs) ? separate instruction bus and load/store bus harvard architecture ? reservation instructions for implem enting read-modify-write constructs ? multi-cycle divide (divw) and load multipl e (lmw) store multiple (smw) multiple class instructions, can be interrupted to pr event increases in interrupt latency ? extensive system developmen t support through nexus debug port
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 12 1.6.3 display control unit (dcu) the dcu is a display controller designed to drive tft lcd displays capable of driving up to wqvga resolution screens with 16 layers and 4 planes with real time alpha-blending. the dcu generates all the necessary signals required to drive the displa y: up to 24-bit rg b data bus, pixel clock, data enable, horizont al-sync and vertical-sync. internal memory resource of the PXD10 allows to ea sily handle complex graphi cs contents (pictures, icons, languages, fonts) on a color tft panel in up to wide quarter video graphics array (wqvga) sizes. all the data fetches from inte rnal and/or external memory are pe rformed by the internal four-channel dma of the dcu providing a high speed/low latency access to the system backbone. control descriptors (cds) associated with each layer enable effective merging of different resolutions into one plane to optimize use of internal memory buffers. a layer may be constructed from graphic content of various resolutions including 1bpp, 2bpp, 4bpp, 8bpp, 16bpp, 24bpp and 24bpp+alpha. the ability of the dcu to handle input data in resolutions as low as 1bpp, 2bpp and 4bpp enables a highly efficient use of internal memory resources of the PXD10. a special tiled mode can be enabled on any of the 16 layers to repeat a pattern optimizi ng graphic memory usage. a hardware cursor can be managed independently of the layers at bl ending level increasing the efficient use of the internal dcu resources. to secure the content of all critical information to be displayed, a safety mode can be activated to check the integrity of critical data along the whole system data path from the memory to the tft pads. the dcu features the following: ? display color depth: up to 24 bpp ? generation of all rgb and control signals for tft ? four-plane blending ? maximum number of input layers: 16 (fixed priority) ? dynamic look-up table (c olor and gamma look-up) ? ?? blending range: as many as 256 levels ? transparency mode ? gamma correction ? tiled mode on all the layers ? hardware cursor ? critical display content integrity m onitoring for functional safety support ? internal direct memory access (d ma) module to transfer data from internal and/or external memory.
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 13 1.6.4 parallel data interface (pdi) the pdi is a digital interface used to receive external digital video or graphic content into the dcu. the pdi input is directly injected into the dcu ba ckground plane fifo. when the pdi is activated, all the dcu synchronization is extracted from the external video stream to guarant ee the synchronization of the two video sources. the pdi can be used to: ? connect a video camera output directly to the pdi ? connect a secondary display driver as slave with a minimum of extra cost ? connect a device gathering various video sources ? provide flexibility to allow the dcu to be used in slave mode (e xternal synchronization) the pdi features the following: ? supported color modes: ? 8-bit mono ? 8-bit color multiplexed ? rgb565 ? 16-bit/18-bit raw color ? supported synchronization modes: ? embedded itu-r bt.656-4 (rgb565 mode 2) ? hsync, vsync ? data enable ? direct interface with dcu background plane fifo ? synchronization generation for the dcu 1.6.5 liquid crystal display (lcd) driver the lcd driver module has two configurations allowing a maximum of 160 or 228 lcd segments: ? as many as 40 frontplane driver s and four backplane drivers ? as many as 38 frontplane drivers and six backplane drivers each segment is controlled and can be masked by a corresponding bit in the lcd ram. four to six multiplex modes (1/1, 1/2, 1/3, 1/4, 1/5, 1/ 6 duty), and three bias (1/1, 1/2, 1/3) methods are available. all frontplane and backplane pins can be multiplexed with other port functions. the lcd driver module fe atures the following: ? programmable frame clock generato r from different clock sources: ? system clock ? internal rc oscillator ? programmable bias vol tage level selector ? on-chip generation of all output voltage levels
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 14 ? lcd voltage reference ta ken from main 5v supply ? lcd ram ? contains the data to be displayed on the lcd ? data can be read from or writte n to the display ram at any time ? end of frame interrupt ? optimizes the refresh of the data without visual artefact ? provides selectable number of frames between each interrupt ? contrast adjustment using program mable internal voltage reference ? remapping capability of four or six backplanes with frontplanes ? increase pin selection flexibility ? in low power modes, the lcd operation can be suspended under software control. the lcd can also operate in low power modes, clocked by the internal 128 khz irc or external 32 khz crystal oscillator ? selectable output current boost during transitions 1.6.6 stepper motor controller (smc) the smc module is a pwm motor controller suitable to drive loads requiring a pwm signal. the motor controller has twelve pwm cha nnels associated with two pi ns each (24 pins in total). the smc module includes the following features: ? 10/11-bit pwm counter ? 11-bit resolution with select able pwm dithering function ? left, right, or center aligned pwm ? output slew rate control ? output short circuit detection this module is suited for, but not limited to, dr iving small stepper and ai r core motors used in instrumentation applications . this module can be used for other motor control or pwm applications that match the frequency, resolution, and out put drive capabilities of the module. 1.6.7 stepper stall detector (ssd) the stepper stall detector (ssd) m odule provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full st eps when the gauge pointer is returning to zero (rtz). the ssd module features the following: ? programmable full step state ? programmable integration polarity ? blanking (recirculation) state ? 16-bit integration accumulator register ? 16-bit modulus down counter with interrupt
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 15 1.6.8 flash memory the PXD10 microcontroller has the fo llowing flash memory features: ? as much as 1 mb of burst flash memory ? typical flash memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer miss at 64 mhz ? two 4 128-bit page buffers with programmable prefetch control ? one set of page buffers can be allocated for c ode-only, fixed partitions of code and data, all available for any access ? one set of page buffers allocated to display controller unit and the edma ? 64-bit ecc with single-bit correction, double-bit detection for data integrity ? 64 kb data flash memory ? separate 4 ? 16 kb flash block for eeprom emulation with prefetch buffer and 128-bit data access port ? small block flash memory arrangement to suppor t features such as boot block, operating system block ? hardware managed flash memory wr ites, erase and verify sequence ? censorship protection scheme to prev ent flash memory content visibility ? separate dedicated 64 kb data flash memory for eeprom emulation ? four erase sectors each c ontaining 16 kb of memory ? offers read-while-write functi onality from main program space ? same data retention and program erase specification as main program flash memory array 1.6.9 static random-access memory (sram) the PXD10 microcontrollers have as much as 48 kb general-purpos e on-chip sram with the following features: ? typical sram access time: 0 wait-s tate for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block ? 32-bit ecc with single-bit correction, double bit detection for data integrity ? supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory ? user transparent ecc encoding and decoding for byte, half word, and word accesses ? separate internal power domain applied to full sram block, 8 kb sram block during standby modes to retain cont ents during low power mode. 1.6.10 on-chip graphics sram the PXD10 microcontroller has 160 kb on-chip gr aphics sram with th e following features: ? usable as general purpose sram ? typical sram access tim e: 0 wait-state for r eads and 32-bit writes ? supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 16 1.6.11 quadspi serial flash controller the quadspi module enables use of external seri al flash memories supporting single, dual and quad modes of operation. it features the following: ? memory mapping of external serial flash ? automatic serial flash read command generation by cpu, dma or dcu r ead access on ahb bus ? supports single, dual and quad serial flash read commands ? flexible buffering scheme to maximi ze read bandwidth of serial flash ? ?legacy? mode allowing quadspi to be used as a standard spi (no dsi or csi mode) 1.6.12 analog-to-digital converter (adc) the adc features the following: ? 10-bit a/d resolution ? 0 to 5 v common mode conversion range ? supports conversions speeds of as fast as 1 s ? 16 internal and 8 external channels support ? as many as 16 single-ended inputs channels ? all channels configured to have alternat e function as general purpose input/output pins ? 10-bit 3 counts accuracy (tue) ? external multiplexer support to in crease as many as 23 channels ? automatic 1 8 mu ltiplexer control ? external multiplexer connected to a dedicated input channel ? shared register between the 8 external channels ? result register available fo r every non-multiplexed channel ? configurable left- or right-aligned result format ? supports for one-shot, scan and injection conversion modes ? injection mode status bit implemented on adjacent 16-bit register for each result ? supports access to result and inject ion status with single 32-bit read ? independently enabling of function for channels: ? pre-sampling ? offset error cancellation ?offset refresh ? conversion triggering support ? internal conversion triggering from periodic interrupt timer (pit) ? four configurable analog comparator channels offering range comparison with triggered alarm ? greater than ?less than ? out of range
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 17 ? all unused analog inputs can be used as general purpose input and output pins ? power down mode ? optional support for dma transfer of results 1.6.13 sound generation logic (sgl) module the sgl module has two modes of operation: ? amplitude modulated pwm mode for low co st buzzers using any two emios channels ? monophonic signal with amplitude control ? 8-bit amplitude resolution ? ability to mix any two emios channels. ? requires simple external rc lowpass filter ? digital sample mode for higher quality sound using one emios channel and edma ? up to 10-bit audio amplitude resolution ? polyphonic sound synthesis ? playback of sample based waveforms ? text-to-speech possibility ? requires external lowpass filter 1.6.14 serial communication interface module (uart) the PXD10 devices include as many as two uart modules and support uart master mode, uart slave mode and uart mode. the modules are uart state machine compliant to the uart 1.3 and 2.0 and 2.1 specifications and handle uart frame tran smission and reception without cpu intervention. the serial communication interf ace module offers the following: ? uart features: ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation wi th four interrupts sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate modul us counter and 16-bit fractional ? two receiver wake-up methods ? lin features: ? autonomous lin frame handling ? message buffer to stor e identifier and as many as 8 data bytes
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 18 ? supports message length of as long as 64 bytes ? detection and flagging of lin errors ? sync field; delimiter; id parity; bit, framing; checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back ?self test ? lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? discarding of irrelevant lin responses using as many as 16 id filters 1.6.15 serial peripheral interface (spi) module the spi modules provide a synchronous serial inte rface for communication betw een the PXD10 mcu and external devices. the spi features the following: ? as many as two spi modules ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data frames from four to 16 bits ? as many as six chip select lines available, depending on packag e and pin multiplexing, enable 64 external devices to be selected us ing external muxing from a single spi ? eight clock and transfer attributes registers ? chip select strobe available as alternate functi on on one of the chip select pins for deglitching ? fifos for buffering as many as four tr ansfers on the transmit and receive side ? general purpose i/o functionality on pins when not used for spi ? queueing operation possible through use of edma
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 19 1.6.16 controller area ne twork (can) module the PXD10 contains two can modules that offer the following features: ? compliant with can protocol specification, version 2.0b active ? 64 mailboxes, each configurab le as transmit or receive ? mailboxes configurable while modul e remains synchronized to can bus ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to me ssage id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort proce dure and notification ? receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo ? 8 programmable acceptance filters for receive fifo ? programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter ? listen only mode capabilities ?can sampler ? can catch the first message sent on the can network while the PXD10 is stopped. this guarantees a clean startup of the system without missing message s on the can network. ? the can sampler is connected to one of the can rx pins. 1.6.17 inter-ic communications (i 2 c) module the i 2 c module features the following: ? as many as four i 2 c modules supported ? two-wire bi-directional serial bus for on-board communications ? compatibility with i 2 c bus standard ? multimaster operation ? software-programmable for one of 256 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus-busy detection
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 20 1.6.18 real time counter (rtc) the real timer counter supports wake-up from lo w power modes or real time clock generation ? configurable resolution for different timeout periods ? 1 s resolution for >1 hour period ? 1 ms resolution for 2 second period ? selectable clock sources from external 32 khz crystal, extern al 4?16 mhz crystal, internal 128 khz rc oscillator or divide d internal 16 mhz rc oscillator 1.6.19 enhanced modular input/ output system (timers, pwm) PXD10 microcontrollers have two emios modules ?one with 16 channels and one with 8?with input/output channels supporting a range of 16-bit input capture, out put compare, and pulse width modulation functions. the modules are configurable and can implement 8-channel, 16-bit input capture/output compare or 16-channel, 16-bit output pulse wi dth modulation/input compare/output compare. as many as five additional channels are confi gurable as modulus counters. emios features include: ? selectable clock source from main fmpll, a uxiliary fmpll, external 4?16 mhz oscillator or 16 mhz internal rc oscillator ? timed i/o channels with 16-bit counter resolution ? buffered updates ? support for shifted pwm outputs to mini mize occurrence of concurrent edges ? edge aligned output pulse width modulation ? programmable pulse pe riod and duty cycle ? supports 0% and 100% duty cycle ? shared or independent time bases ? programmable phase sh ift between channels ? selectable combination of pairs of emios outputs to support sound generation ? dma transfer support ? selectable clock source from the primary fmpll, auxiliar y fmpll, external 4?16 mhz oscillator or the 16 mhz internal rc oscillator. the channel configuration options for the 16-channel emios module are summarized in table 2 .
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 21 the channel configuration options for the 8-channel emios module are summarized in table 3 . 1.6.20 periodic interrupt timer (pit) module the pit features the following: ? four general purpos e interrupt timers ? as many as two dedicated interrupt timers for triggering adc conversions ? 32-bit counter resolution ? clocked by system clock frequency ? 32-bit counter for real time interrupt, clocked from main external oscillator table 2. 16-channel emios module channel configuration channel mode channel number 8 ic/oc counter 9?15 ic/oc 16 pwm counter 17?22 pwm 23 pwm counter general purpose input/output xxxxx single action input capture xxxxx single action output compare xxxxx modulus counter buffered 1 notes: 1 modulus up and down counters to support driving local and global counter busses xxx output pulse width and frequency modulation buffered x x x output pulse width modulation buffered x x x table 3. 8-channel emios module channel configuration channel mode channel number 16 pwm counter 17?22 pwm 23 pwm counter general purpose input/output x x x single action input capture x x x single action output compare x x x modulus counter buffered 1 notes: 1 modulus up and down counters to support driving local and global counter busses xx output pulse width and frequency modulation buffered x x x output pulse width modulation buffered x x x
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 22 1.6.21 system timer module (stm) the stm is a 32-bit timer that supports commonly required system and application software timing functions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 1.6.22 software watchdog timer (swt) the swt features the following: ? watchdog supporting software acti vation or enabled out of reset ? supports normal or windowed mode ? watchdog timer value wr itable once after reset ? watchdog supports optional ha lting during low power modes ? configurable response on timeout: reset, in terrupt, or interrupt followed by reset ? selectable clock source for main system cl ock or internal 16 mhz rc oscillator clock 1.6.23 interrupt controller (intc) the intc provides priority-based preemptive scheduli ng of interrupt requests, suitable for statically scheduled hard real-time systems. for high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executi ng the interrupt service routine (i sr) has been minimized. the intc provides a unique vector for each inte rrupt request source for quick dete rmination of which isr needs to be executed. it also provides an ample number of prior ities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropria te priorities for each s ource of interrupt request, the priority of each interrupt re quest is software configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providi ng a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. multiple processors can assert interrupt requests to each other through software settable interrupt requests. these same software settable interrupt requests also ca n be used to break the work involved in servicing an interrupt request into a high priority po rtion and a low priority portion. the high priority porti on is initiated by a peripheral interrupt request, but then the isr asserts a so ftware settable interrupt reque st to finish the servicing in a lower priority isr. therefore these software settable interrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. the intc provides the following features: ? unique 9-bit vector for each of the po ssible 128 separate interrupt sources ? eight software-triggerable interrupt sources
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 23 ? 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source ? ability to modify the isr or task priority. ? modifying the priority can be used to implem ent the priority ceiling protocol for accessing shared resources. ? external non-maskable in terrupt directly accessing the main core cri tical interrupt mechanism ? 32 external interrupts 1.6.24 system integration unit (siu) the siu controls mcu reset confi guration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiple xing, and the system reset operation. the gpio features the following: ? as many as four levels of internal pin mul tiplexing, allowing exceptional flexibility in the allocation of device functions for each package ? centralized general purpose input output (gpio) control of as many as 132 input/output pins (package dependent) ? all gpio pins can be independently conf igured to support pul l-up, pull down, or no pull ? reading and writing to gpio supported both as individual pins and 16-bit wide ports ? all peripheral pins can be alte rnatively configured as both gene ral purpose input or output pins except adc channels which support alternative configurat ion as general purpose inputs ? direct readback of the pin value supported on all digita l output pins through the siu ? configurable digital input filter that can be applied to as many as 14 general purpose input pins for noise elimination on external interrupts ? register configuration protected ag ainst change with soft lock for temporary guard or hard lock to prevent modification until next reset. 1.6.25 system clocks and clock generation modules the system clock on the PXD10 can be derived from an external oscillator, an on-chip fmpll, or the internal 16 mhz oscillator. ? the source system clock freque ncy can be changed via an on-ch ip programmable clock divider ( ? 1 to ?? 2). ? additional programmabl e peripheral bus cl ock divider ratio ( ? 1 to ? 16) ? the PXD10 has two on-chip fmplls?the primary module and an auxiliary module. ? each features the following: ? input clock frequency from 4 mhz to 16 mhz ? lock detect circuitry conti nuously monitors lock status ? loss of clock (loc) detection fo r reference and feedback clocks ? on-chip loop filter (for impr oved electromagnetic interfer ence performance and reduction of number of external components required)
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 24 ? support for frequency ramping from pll ? the primary fmpll module is for use as a system clock s ource. the auxiliary fmpll is available for use as an altern ate, modulated or non-modulated clock source to emios modules and as alternate clock to the dcu for pixel clock generation. ? the main oscillator provides the following features: ? input frequency range 4?16 mhz ? square-wave input mode ? oscillator input mode 3.3 v (5.0 v) ? automatic level control ? pll reference ? PXD10 includes a 32 khz low power external oscillator for slow execution, low power, and real time clock ? dedicated internal 128 khz rc oscillator fo r low power mode operation and self wake-up ? 10% accuracy across vol tage and temperature (a fter factory trimming) ? trimming registers to suppor t improved accuracy with in-application calibration ? dedicated 16 mhz inte rnal rc oscillator ? used as default clock source out of reset ? provides a clock for rapid st art-up from low power modes ? provides a back-up clock in the event of pll or external oscillator clock failure ? offers an independent clock source for the watchdog timer ? 5% accuracy across voltage and te mperature (after factory trimming) ? trimming registers to support frequency ad justment with in-appl ication calibration 1.6.26 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connections between four master ports and four slave ports. the crossbar supports a 32-bi t address bus width and a 32-bit data bus width. the crossbar allows four concurrent transactions to occur from any ma ster port to any slave port but one of those transfers must be an inst ruction fetch from internal flash. if a slave port is simultaneously requested by more than one master por t, arbitration logic selects the highe r priority master and grants it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. requesting masters having equal priori ty are granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access. the crossbar provides the following features: ? four master ports ? e200z0h core instruction port ? e200z0h core complex load/store data port ? edma controller ? display control unit
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 25 ? four slave ports ? one flash port dedicated to the cpu ? platform sram ? quadspi serial flash controller ? one slave port combining: ? flash port dedicated to the disp lay control unit and edma module ? graphics sram ? peripheral bridge ? 32-bit internal address bus , 32-bit internal data bus 1.6.27 enhanced direct memory access (edma) the edma module is a controller capable of performing complex da ta movements via 16 programmable channels, with minimal intervention from the host processor. the hardware micro architecture includes a dma engine which performs source and destination address calculations , and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is utilized to minimize the overall bl ock size. the edma module provides the following features: ? 16 channels support independent 8-, 16- or 32-bit single value or block transfers ? supports variable sized que ues and circular queues ? source and destination address regi sters are independently configured to post-increment or remain constant ? each transfer is initiated by a peripheral, cpu, periodic timer interrupt or edma channel request ? each dma channel can optionally send an interrupt request to th e cpu on completion of a single value or block transfer ? dma transfers possible between sy stem memories, quadspi, spis, i 2 c, adc, emios and general purpose i/os (gpios) ? programmable dma channel mux allows assignm ent of any dma source to any available dma channel with a total of as many as 64 potential request sources. 1.6.28 memory protection unit (mpu) the mpu features the following: ? 12 region descriptors for per-master protection ? start and end address defi ned with 32-byte granularity ? overlapping regions supported ? protection attributes can optionally include process id ? protection offered for 3 concurrent read ports ? read and write attri butes for all masters ? execute and supervisor/user mode attributes for processor masters
overview PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 26 1.6.29 boot assist module (bam) the bam is a block of read-only memory that is programmed once by freescale. the bam program is executed every time the mcu is powered-on or reset in normal mode. the bam s upports different modes of booting. they are: ? booting from internal flash memory ? serial boot loading (a program is downloaded into ram via can or uart and then executed) ? booting from external memory additionally, the bam: ? enables and manages the transition of the mcu from reset to user code execution ? configures device for serial bootload ? enables multiple bootcode starting locations out of reset through implem entation of search for valid reset configuration halfword ? enables or disables software watchdog timer out of reset through ba m read of the reset configuration halfword option bit 1.6.30 ieee 1149.1 jtag controller (jtagc) jtagc features the following: ? backward compatible to standard jtag ie ee 1149.1-2001 test access port (tap) interface ? support for boundary scan testing 1.6.31 nexus development interface (ndi) nexus features the following: ? per ieee-isto 5001-2003 ? nexus 2 plus features supported ? static debug ? watchpoint messaging ? ownership trace messaging ? program trace messaging ? real time read/write of any internally memory mapped resources through jtag pins ? overrun control, which selects whether to stal l before nexus overruns or keep executing and allow overwrite of information ? watchpoint triggering, watchpoint triggers program tracing ? configured via the ieee 1149.1 (jtag) port ? nexus auxiliary port supported on the 176 lqfp package for development only ? narrow auxiliary nexus port supporti ng support trace, with two mdo pins ? wide auxiliary nexus port supporting higher bandwidth trace, with four mdo pins
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 27 2 pinout and signal descriptions 2.1 144 lqfp package pinouts this section shows the pinouts for the 144-pin lqfp packages. caution any pins labeled ?nc? must not be connected to any external circuit. figure 2. 144-pin lqfp pinout for PXD1010 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144-pin lqfp PXD1010 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi/gpio[72]/pf2 vdde_b vsse_b pcs2_0/emiosb19/rxd_1/gpio[28]/pb12 pcs1_0/emiosb18/txd_1/gpio[29]/pb13 vdd12 vss12 emiosb20/sck_0/gpio[25]/pb9 emiosb21/sout_0/gpio[24]/pb8 emiosb22/sin_0/gpio[23]/pb7 clkout/emiosb16/pcs0_0/gpio[103]/ph4 ma0/sck_1/gpio[20]/pb4 fabm/ma1/sout_1/gpio[21]/pb5 abs[0]/ma2/sin_1/gpio[22]/pb6 vdd12 vss12 vdda vssa xtal32/ans15/gpio[45]/pc15 extal32/ans14/gpio[44]/pc14 pcs0_1/ma2/ans13/gpio[43]/pc13 pcs1_1/ma1/ans12/gpio[42]/pc12 pcs2_1/ma0/ans11/gpio[41]/pc11 sound/ans10(mux)/gpio[40]/pc10 ans9/gpio[39]/pc9 ans8/gpio[38]/pc8 vdde_c vsse_c ans7/gpio[37]/pc7 ans6/gpio[36]/pc6 ans5/gpio[35]/pc5 ans4/gpio[34]/pc4 ans3/gpio[33]/pc3 ans2/gpio[32]/pc2 ans1/gpio[31]/pc1 ans0/gpio[30]/pc0 pa9/gpio[9]/dcu_g1/emiosb18/sda_2/fp14 pa8/gpio[8]/dcu_g0/emiosb23/scl_2/fp15 pa7/gpio[7]/dcu_r7/emiosa16/fp16 pa6/gpio[6]/dcu_r6/emiosa15/fp17 pa5/gpio[5]/dcu_r5/emiosa17/fp18 pa4/gpio[4]/dcu_r4/emiosa18/fp19 pa3/gpio[3]/dcu_r3/emiosa19/fp20 pa2/gpio[2]/dcu_r2/emiosa20/fp21 pa1/gpio[1]/dcu_r1/emiosa21/fp22 pa0/gpio[0]/dcu_r0/emiosa22/sound/fp23 vss12 vdd12 pf15/gpio[85]/sck_2/fp24 pf14/gpio[84]/sout_2/cantx_1/fp25 pf13/gpio[83]/sin_2/canrx_1/fp26 pf12/gpio[82]/emiosb16/pcs2_2/fp27 pf11/gpio[81]/emiosb23/pcs1_2/fp28 pf10/gpio[80]/emiosa16/pcs0_2/fp29 pg12/gpio[98]/emiosa23/sound/emiosa8/fp vsse_a vdde_a pf9/gpio[79]/scl_1/pcs0_1/txd_1/fp31 pf8/gpio[78]/sda_1/pcs1_1/rxd_1/fp32 pf7/gpio[77]/scl_0/pcs2_1/fp33 pf6/gpio[76]/sda_0/fp34 vss12 vdd12 pf5/gpio[75]/emiosa9/dcu_tag/fp35 pf4/gpio[74]/emiosa10/pdi7/fp36 pf3/gpio[73]/emiosa11/pdi6/fp37 pf1/gpio[71]/emiosa12/pdi5/emiosa21/fp38 pf0/gpio[70]/emiosa13/pdi4/emiosa22/fp39 pb2/gpio[18]/txd_0 pb3/gpio[19]/rxd_0 vsse_e vdde_e pb11/gpio[27]/cantx_1/pdi3/emiosa16 pb10gpio[26]//canrx_1/pdi2/emiosa23 pb0/gpio[16]/cantx_0/pdi1 pb1/gpio[17]/canrx_0/pdi0 vss12 vdd12 pe7/gpio[69]/m5c1p/ssd5_3/emiosa8 pe6/gpio[68]/m5c1m/ssd5_2/emiosa9 pe5/gpio[67]/m5c0p/ssd5_1/emiosa10 pe4/gpio[66]/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/gpio[65]/m4c1p/ssd4_3/emiosa12 pe2/gpio[64]/m4c1m/ssd4_2/emiosa13 pe1/gpio[63]/m4c0p/ssd4_1/emiosa14 pe0/gpio[62]/m4c0m/ssd4_0/emiosa15 pd15/gpio[61]/m3c1p/ssd3_3 pd14/gpio[60]/m3c1m/ssd3_2 pd13/gpio[59]/m3c0p/ssd3_1 pd12/gpio[58/m3c0m/ssd3_0 vssmb vddmb pd11/gpio[57]/m2c1p/ssd2_3 pd10/gpio[56]/m2c1m/ssd2_2 pd9/gpio[55]/m2c0p/ssd2_1 pd8/gpio[54]/m2c0m/ssd2_0 pd7/gpio[53]/m1c1p/ssd1_3/emiosb16 pd6/gpio[52]/m1c1m/ssd1_2/emiosb17 pd5/gpio[51]/m1c0p/ssd1_1/emiosb18 pd4/gpio[50]/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/gpio[49]/m0c1p/ssd0_3/emiosb20 pd2/gpio[48]/m0c1m/ssd0_2/emiosb21 pd1/gpio[47]/m0c0p/ssd0_1/emiosb22 pd0/gpio[46]/m0c0m/ssd0_0/emiosb23 (see detail inset) pa10 (see detail inset) pa11 (see detail inset) pa12 (see detail inset) pa13 (see detail inset) pa14 (see detail inset) pa15 vdde_a vsse_a (see detail inset) pg0 fp6/sda_3/dcu_b1/gpio[87]/pg1 (see detail inset) pg2 (see detail inset) pg3 (see detail inset) pg4 fp2/emiosa8/dcu_b5/gpio[91]/pg5 fp1/dcu_b6/gpio[92]/pg6 fp0/dcu_b7/gpio[93]/pg7 bp0/dcu_vsync/gpio[94]/pg8 bp1/dcu_hsync/gpio[95]/pg9 bp2/dcu_de/gpio[96]/pg10 bp3/dcu_pclk/gpio[97]/pg11 vlcd/gpio[104]/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll vreg_bypass tdi/gpio[100]/ph1 tdo/gpio[101]/ph2 tms/gpio[102]/ph3 tck/gpio[99]/ph0 detail: fp13/emiosb20/dcu_g2/gpio[10]/pa10 ? fp12/emiosa13/dcu_g3/gpio[11]/pa11 ? fp11/emiosa12/dcu_g4/gpio[12]/pa12 ? fp10/emiosa11/dcu_g5/gpio[13]/pa13 ? fp9/emiosa10/dcu_g6/gpio[14]/pa14 ? fp8/emiosa9/dcu_g7/gpio[15]/pa15 ? fp7/sound/scl_3/dcu_b0/gpio[86]/pg0 ? fp5/emiosb19/dcu_b2/gpio[88]/pg2 ? fp4/emiosb21/dcu_b3/gpio[89]/pg3 ? fp3/emiosb17/dcu_b4/gpio[90]/pg4 ?
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 28 figure 3. 144-pin lqfp pinout for PXD1005 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi/gpio[72]/pf2 vdde_b vsse_b pcs2_0/emiosb19/rxd_1/gpio[28]/pb12 pcs1_0/emiosb18/txd_1/gpio[29]/pb13 vdd12 vss12 emiosb20/sck_0/gpio[25]/pb9 emiosb21/sout_0/gpio[24]/pb8 emiosb22/sin_0/gpio[23]/pb7 clkout/emiosb16/pcs0_0/gpio[103]/ph4 ma0/sck_1/gpio[20]/pb4 fabm/ma1/sout_1/gpio[21]/pb5 abs[0]/ma2/sin_1/gpio[22]/pb6 vdd12 vss12 vdda vssa xtal32/ans15/gpio[45]/pc15 extal32/ans14/gpio[44]/pc14 pcs0_1/ma2/ans13/gpio[43]/pc13 pcs1_1/ma1/ans12/gpio[42]/pc12 pcs2_1/ma0/ans11/gpio[41]/pc11 sound/ans10(mux)/gpio[40]/pc10 ans9/gpio[39]/pc9 ans8/gpio[38]/pc8 vdde_c vsse_c ans7/gpio[37]/pc7 ans6/gpio[36]/pc6 ans5/gpio[35]/pc5 ans4/gpio[34]/pc4 ans3/gpio[33]/pc3 ans2/gpio[32]/pc2 ans1/gpio[31]/pc1 ans0/gpio[30]/pc0 pa9/gpio[9]/emiosb18/fp14 pa8/gpio[8]/emiosb23/fp15 pa7/gpio[7]/emiosa16/fp16 pa6/gpio[6]/emiosa15/fp17 pa5/gpio[5]/emiosa17/fp18 pa4/gpio[4]/emiosa18/fp19 pa3/gpio[3]/emiosa19/fp20 pa2/gpio[2]/emiosa20/fp21 pa1/gpio[1]/emiosa21/fp22 pa0/gpio[0]/emiosa22/sound/fp23 vss12 vdd12 pf15/gpio[85]/fp24 pf14/gpio[84]/cantx_1/fp25 pf13/gpio[83]/canrx_1/fp26 pf12/gpio[82]/emiosb16/fp27 pf11/gpio[81]/emiosb23/fp28 pf10/gpio[80]/emiosa16/fp29 pg12/gpio[98]/emiosa23/sound/emiosa8/fp30 vsse_a vdde_a pf9/gpio[79]/scl_1/pcs1_0/txd_1/fp31 pf8/gpio[78]/sda_1/pcs1_1/rxd_1/fp32 pf7/gpio[77]/scl_0/pcs2_1/fp33 pf6/gpio[76]/sda_0/fp34 vss12 vdd12 pf5/gpio[75]/emiosa9/fp35 pf4/gpio[74]/emiosa10/fp36 pf3/gpio[73]/emiosa11/fp37 pf1/gpio[71]/emiosa12/emiosa21/fp38 pf0/gpio[70]/emiosa13/emiosa22/fp39 pb2/gpio[18]/txd_0 pb3/gpio[19]/rxd_0 vsse_e vdde_e pb11/gpio[27]/cantx_1/emiosa16 pb10gpio[26]//canrx_1/emiosa23 pb0/gpio[16]/cantx_0 pb1/gpio[17]/canrx_0 vss12 vdd12 pe7/gpio[69]/m5c1p/ssd5_3/emiosa8 pe6/gpio[68]/m5c1m/ssd5_2/emiosa9 pe5/gpio[67]/m5c0p/ssd5_1/emiosa10 pe4/gpio[66]/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/gpio[65]/m4c1p/ssd4_3/emiosa12 pe2/gpio[64]/m4c1m/ssd4_2/emiosa13 pe1/gpio[63]/m4c0p/ssd4_1/emiosa14 pe0/gpio[62]/m4c0m/ssd4_0/emiosa15 pd15/gpio[61]/m3c1p/ssd3_3 pd14/gpio[60]/m3c1m/ssd3_2 pd13/gpio[59]/m3c0p/ssd3_1 pd12/gpio[58/m3c0m/ssd3_0 vssmb vddmb pd11/gpio[57]/m2c1p/ssd2_3 pd10/gpio[56]/m2c1m/ssd2_2 pd9/gpio[55]/m2c0p/ssd2_1 pd8/gpio[54]/m2c0m/ssd2_0 pd7/gpio[53]/m1c1p/ssd1_3/emiosb16 pd6/gpio[52]/m1c1m/ssd1_2/emiosb17 pd5/gpio[51]/m1c0p/ssd1_1/emiosb18 pd4/gpio[50]/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/gpio[49]/m0c1p/ssd0_3/emiosb20 pd2/gpio[48]/m0c1m/ssd0_2/emiosb21 pd1/gpio[47]/m0c0p/ssd0_1/emiosb22 pd0/gpio[46]/m0c0m/ssd0_0/emiosb23 (see detail inset) pa10 (see detail inset) pa11 (see detail inset) pa12 (see detail inset) pa13 (see detail inset) pa14 (see detail inset) pa15 vdde_a vsse_a (see detail inset) pg0 fp6/gpio[87]/pg1 (see detail inset) pg2 (see detail inset) pg3 (see detail inset) pg4 fp2/emiosa8/gpio[91]/pg5 fp1/gpio[92]/pg6 fp0/gpio[93]/pg7 bp0/gpio[94]/pg8 bp1/gpio[95]/pg9 bp2/gpio[96]/pg10 bp3/gpio[97]/pg11 vlcd/gpio[104]/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll vreg_bypass tdi/gpio[100]/ph1 tdo/gpio[101]/ph2 tms/gpio[102]/ph3 tck/gpio[99]/ph0 detail: fp13/emiosb20/gpio[10]/pa10 ? fp12/emiosa13/gpio[11]/pa11 ? fp11/emiosa12/gpio[12]/pa12 ? fp10/emiosa11/gpio[13]/pa13 ? fp9/emiosa10/gpio[14]/pa14 ? fp8/emiosa9/gpio[15]/pa15 ? fp7/sound/gpio[86]/pg0 ? fp5/emiosb19/gpio[88]/pg2 ? fp4/emiosb21/gpio[89]/pg3 ? fp3/emiosb17/gpio[90]/pg4 ? 144-pin lqfp PXD1005
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 29 2.2 176 lqfp package pinout figure 4 shows the pinout for the 176-pin lqfp package. caution any pins labeled ?nc? must not be connected to any external circuit. figure 4. 176-pin lqfp pinout 176-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pa9/gpio[9]/dcu_g1/emiosb18/sda_2/fp14 pa8/gpio[8]/dcu_g0/emiosb23/scl_2/fp15 pa7/gpio[7]/dcu_r7/emiosa16/fp16 pa6/gpio[6]/dcu_r6/emiosa15/fp17 pa5/gpio[5]/dcu_r5/emiosa17/fp18 vsse_a vdde_a pa4/gpio[4]/dcu_r4/emiosa18/fp19 pa3/gpio[3]/dcu_r3/emiosa19/fp20 pa2/gpio[2]/dcu_r2/emiosa20/fp21 pa1/gpio[1]/dcu_r1/emiosa21/fp22 pa0/gpio[0]/dcu_r0/emiosa22/sound/fp23 vss12 vdd12 pf15/gpio[85]/sck_2/fp24 pf14/gpio[84]/sout_2/cantx_1/fp25 pf13/gpio[83]/sin_2/canrx_1/fp26 pf12/gpio[82]/emiosb16/pcs2_2/fp27 pf11/gpio[81]/emiosb23/pcs1_2/fp28 pf10/gpio[80]/emiosa16/pcs0_2/fp29 pg12/gpio[98]/emiosa23/sound/emiosa8/fp30 vsse_a vdde_a pf9/gpio[79]/scl_1/pcs0_1/txd_1/fp31 pf8/gpio[78]/sda_1/pcs1_1/rxd_1/fp32 pf7/gpio[77]/scl_0/pcs2_1/fp33 pf6/gpio[76]/sda_0/fp34 vss12 vdd12 pf5/gpio[75]/emiosa9/dcu_tag/fp35 pf4/gpio[74]/emiosa10/pdi7/fp36 pf3/gpio[73]/emiosa11/pdi6/fp37 pf1/gpio[71]/emiosa12/pdi5/emiosa21/fp38 pf0/gpio[70]/emiosa13/pdi4/emiosa22/fp39 pk1/gpio[122]/pdi13/emiosa17 pk0/gpio[121]/pdi12/emiosa18/dcu_tag pb2/gpio[18]/txd_0 pb3/gpio[19]/rxd_0 pj15/gpio[120]/pdi11/emiosa19 pj14/gpio[119]/pdi10/emiosa20 pj13/gpio[118]/pdi9/emiosb20 pj12/gpio[117]/pdi8/emiosb17 vsse_e vdde_e nmi/gpio[72]/pf2 vdde_b vsse_b pcs2_0/emiosb19/rxd_1/gpio[28]/pb12 pcs1_0/emiosb18/txd_1/gpio[29]/pb13 vdd12 vss12 emiosa15/sda_1/gpio[131]/pk10 emiosa14/scl_1/gpio[132]/pk11 emiosb20/sck_0/gpio[25]/pb9 emiosb21/sout_0/gpio[24]/pb8 emiosb22/sin_0/gpio[23]/pb7 canrx_0/pdi0/gpio[109]/pj4 cantx_0/pdi1/gpio[110]/pj5 emiosa22/canrx_1/pdi2/gpio[111]/pj6 emiosa21/cantx_1/pdi3/gpio[112]/pj7 clkout/emiosb16/pcs0_0/gpio[103]/ph4 ma0/sck_1/gpio[20]/pb4 fabm/ma1/sout_1/gpio[21]/pb5 vdde_b vsse_b abs[0]/ma2/sin_1/gpio[22]/pb6 vdd12 vss12 vdda vssa xtal32/ans15/gpio[45]/pc15 extal32/ans14/gpio[44]/pc14 pcs0_1/ma2/ans13/gpio[43]/pc13 pcs1_1/ma1/ans12/gpio[42]/pc12 pcs2_1/ma0/ans11/gpio[41]/pc11 sound/ans10(mux)/gpio[40]/pc10 ans9/gpio[39]/pc9 ans8/gpio[38]/pc8 vdde_c vsse_c ans7/gpio[37]/pc7 ans6/gpio[36]/pc6 ans5/gpio[35]/pc5 ans4/gpio[34]/pc4 ans3/gpio[33]/pc3 ans2/gpio[32]/pc2 ans1/gpio[31]/pc1 ans0/gpio[30]/pc0 pb11/gpio[27]/cantx_1/pdi3/emiosa16 pb10/gpio[26]/canrx_1/pdi2/emiosa23 pb0/gpio[16]/cantx_0/pdi1 pb1/gpio[17]/canrx_0/pdi0 pj11/gpio[116]/pdi7 pj10/gpio[115]/pdi6 pj9/gpio[114]/pdi5 pj8/gpio[113]/pdi4 vss12 vdd12 pj3/gpio[108]/pdi_pclk pj2/gpio[107]/pdi_vsync pj1/gpio[106]/pdi_hsync pj0/gpio[105]/pdi_de pe7/gpio[69]/m5c1p/ssd5_3/emiosa8 pe6/gpio[68]/m5c1m/ssd5_2/emiosa9 pe5/gpio[67]/m5c0p/ssd5_1/emiosa10 pe4/gpio[66]/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/gpio[65]/m4c1p/ssd4_3/emiosa12 pe2/gpio[64]/m4c1m/ssd4_2/emiosa13 pe1/gpio[63]/m4c0p/ssd4_1/emiosa14 pe0/gpio[62]/m4c0m/ssd4_0/emiosa15 pd15/gpio[61]/m3c1p/ssd3_3 pd14/gpio[60]/m3c1m/ssd3_2 pd13/gpio[59]/m3c0p/ssd3_1 pd12/gpio[58]/m3c0m/ssd3_0 vssmb vddmb pd11/gpio[57]/m2c1p/ssd2_3 pd10/gpio[56]/m2c1m/ssd2_2 pd9/gpio[55]/m2c0p/ssd2_1 pd8/gpio[54]/m2c0m/ssd2_0 pd7/gpio[53]/m1c1p/ssd1_3/emiosb16 pd6/gpio[52]/m1c1m/ssd1_2/emiosb17 pd5/gpio[51]/m1c0p/ssd1_1/emiosb18 pd4/gpio[50]/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/gpio[49]/m0c1p/ssd0_3/emiosb20 pd2/gpio[48]/m0c1m/ssd0_2/emiosb21 pd1/gpio[47]/m0c0p/ssd0_1/emiosb22 pd0/gpio[46]/m0c0m/ssd0_0/emiosb23 (see detail inset) pa10 (see detail inset) pa11 (see detail inset) pa12 (see detail inset) pa13 (see detail inset) pa14 (see detail inset) pa15 vdde_a vsse_a (see detail inset) pg0 (see detail inset) pg1 (see detail inset) pg2 (see detail inset) pg3 (see detail inset) pg4 (see detail inset) pg5 fp1/dcu_b6/gpio[92]/pg6 fp0/dcu_b7/gpio[93]/pg7 (see detail inset) pg8 (see detail inset) pg9 bp2/dcu_de/gpio[96]/pg10 (see detail inset) pg11 vlcd/gpio[104]/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll vreg_bypass pdi10/mcko/gpio[123]/pk2 pdi11/mseo/gpio[124]/pk3 pdi12/evto/gpio[125]/pk4 tdi/gpio[100]/ph1 pdi13/evti/gpio[126]/pk5 pdi14/mdo0/gpio[127]/pk6 tdo/gpio[101]/ph2 pdi15/mdo1/gpio[128]/pk7 tms/gpio[102]/ph3 pdi16/mdo2/gpio[129]/pk8 tck/gpio[99]/ph0 pdi17/mdo3/gpio[130]/pk9 detail: fp13/emiosb20/dcu_g2/gpio[10]/pa10 ? fp12/emiosa13/dcu_g3/gpio[11]/pa11 ? fp11/emiosa12/dcu_g4/gpio[12]/pa12 ? fp10/emiosa11/dcu_g5/gpio[13]/pa13 ? fp9/emiosa10/dcu_g6/gpio[14]/pa14 ? fp8/emiosa9/dcu_g7/gpio[15]/pa15 ? fp7/sound/scl_3/dcu_b0/gpio[86]/pg0 ? fp6/sda_3/dcu_b1/gpio[87]/pg1 ? fp5/emiosb19/dcu_b2/gpio[88]/pg2 ? fp4/emiosb21/dcu_b3/gpio[89]/pg3 ? fp3/emiosb17/dcu_b4/gpio[90]/pg4 ? fp2/emiosa8/dcu_b5/gpio[91]/pg5 ? bp0/dcu_vsync/gpio[94]/pg8 ? bp1/dcu_hsync/gpio[95]/pg9 ? bp3/dcu_pclk/gpio[97]/pg11 ?
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 30 2.3 pad configuration during reset phases all pads have a fixed c onfiguration under reset. during the power-up phase, all pa ds are forced to tristate. after power-up phase, all pads are fl oating with the following exceptions: ? pb[5] (fab) is pull-down. without external str ong pullup the device starts fetching from flash. ? reset pad is driven low. this is re leased only after phase2 reset completion. ? main oscillator pads (extal, xtal) are tristate. ? nexus output pads (mdo[n], mcko, evto, mseo) are forced to output. ? the following pads are pullup: ?pb[6] ?ph[0] ?ph[1] ?ph[3] ?evti 2.4 voltage supply pins voltage supply pins are used to provide power to the device. two dedicated pins are used for 1.2 v regulator stabilization. there is a preferred power-up sequen ce for devices in the PXD10 family . that sequence is described in the following paragraphs. broadly, the supply voltages can be grouped as follows: ? vreg hv supply (v ddr ) ? generic i/o supply ?v dda ?v dde_a ?v dde_b ?v dde_c ?v dde_e ?v ddma ?v ddmb ?v ddmc ?v ddpll ? lv supply (v dd12 ) the preferred order of ramp up is as follows: 1. generic i/o supply
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 31 2. vreg hv supply (v ddr - should be the last hv supply to ramp up. it is also ok if all hv and generic i/o supplies including v ddr ramp up together) 3. lv supply the reason for following this sequence is to ensure that when vreg releases its lvds, the i/o and other hv segments are powered properly. this is importa nt because the PXD10 does not monitor lvds on i/o hv supplies. 2.5 pad types the pads available for system pins a nd functional port pins are described in: ? the port pin summary table ? the pad type descriptions table 2. voltage supply pin descriptions supply pin function pin number 144 lqfp 176 lqfp vdd12 1 notes: 1 decoupling capacitors must be connected between these pins and the nearest v ss12 pin. 1.2 v core supply 42, 51, 103, 118 , 133 50, 67, 123, 148, 163 vdda 3.3 v/5 v adc supply source 53 69 vdde_a 3.3 v/5 v i/o supply 7, 124 7, 154, 170 vdde_b 3.3 v/5 v i/o supply 38 46, 64 vdde_c 3.3 v/5 v i/o supply 63 79 vdde_e 3.3 v/5 v i/o supply 109 133 vddma 2 2 all stepper motor supplies need to be at same level (3.3 v or 5 v). motor pads 5 v supply 77 93 vddmb 2 motor pads 5 v supply 87 103 vddmc 2 motor pads 5 v supply 97 113 vddpll 1.2 v pll supply 31 31 vddr vreg reg supply 22 22 vpp 3 3 this signal needs to be connected to ground during normal operation. 9 v - 12 v flash test analog write signal 26 26 vss digital ground 8, 23, 39, 43, 52, 64, 104, 110, 119, 125, 134 8, 23, 47, 51, 68, 80, 124, 134, 149, 155, 164, 65, 171 vssa adc ground 54 70 vssma stepper motor ground 78 94 vssmb stepper motor ground 88 104 vssmc stepper motor ground 98 114 vssosc mhz oscillator ground 28 28 vsspll pll ground 30 30
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 32 ? the description of the pad configuration registers in chapter 37, system integration unit lite (siul) ? the device data sheet 2.6 system pins the system pins are listed in table 3 . 2.7 debug pins the debug pins are listed in table 4 and table 5 . table 3. system pin descriptions system pin function i/o direction pad type reset config pin no. 144 lqfp 176 lqfp 208 mapbg a reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pull up 24 24 j1 extal analog output of the oscillator amplifier circuit. input for the clock generator in bypass mode. x ? 29 29 m1 xtal analog input of the oscillator amplifier circuit. needs to be grounded if oscillator bypass mode is used. ix ? 27 27 k1 vrc_ctrl vreg ballast control gain ? ? ? 25 25 p1 vreg_ bypass 1 notes: 1 vreg_bypass should be pulled down externally. pin used for factory testing i x ? 32 32 m4 table 4. debug pin descriptions debug pin function pad type i/o direction reset configuration pin number 144 lqfp 176 lqfp 1 208 mapb ga evti nexus event input m i/o none ? 37 a11 evto nexus event output m i/o none ? 35 d12 mcko nexus message clock output f i/o none ? 33 b12 mdo0 nexus message clock output m i/o none ? 38 b11
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 33 mdo1 nexus message clock output m i/o none ? 40 c11 mdo2 nexus message clock output m i/o none ? 42 d11 mdo3 nexus message clock output m i/o none ? 44 a10 mseo nexus message clock output m i/o none ? 34 c12 notes: 1 on the 176 lqfp package options the nexus pins are multiplexed with other gpio. on the 208 tepbga package, there are additional dedicated nexus pins. table 5. debug pin descriptions debug pin function pad type i/o direction reset configuration pin number 144 lqfp 176 lqfp tepbga2 08 1 notes: 1 the dedicated (208 pin package only) nexus output pins (message data outputs 0:3 [mdo] and message start/end outputs 0:1 [mseo]) may drive an unknown value (high or low) immediately after power up but before-the 1st clock edge propagates through the device (instead of being weakly pulled low). this may cause high currents if the pins are tied directly to a supply/ground or any low resistance-driver (when used as a general purpose input [gpi] in the application). evti nexus event input m i/o input, pull up ? ? t3 evto nexus event output m i/o input, pull up ? ? r3 mcko nexus message clock output f i/o input, pull up ? ? t1 mdo0 nexus message clock output m i/o input, pull up ? ? t5 mdo1 nexus message clock output m i/o input, pull up ? ? p5 mdo2 nexus message clock output m i/o input, pull up ? ? p4 mdo3 nexus message clock output m i/o input, pull up ? ? l4 mseo nexus message clock output m i/o input, pull up ? ? t2 table 4. debug pin descriptions (continued) debug pin function pad type i/o direction reset configuration pin number 144 lqfp 176 lqfp 1 208 mapb ga
PXD10 microcontroller data sheet, rev. 1 pinout and signal descriptions freescale semiconductor 34 2.8 port pin summary the functional port pins are listed in table 6 . table 6. port pin summary port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp pa[0] pcr[0] option 0 option 1 option 2 option 3 gpio[0] dcu_r0 emiosa[22] sound fp23 siul dcu pwm/timer sound i/o m1 none, none 135 165 pa[1] pcr[1] option 0 option 1 option 2 option 3 gpio[1] dcu_r1 emiosa[21] ? fp22 siul dcu pwm/timer ? i/o m1 none, none 136 166 pa[2] pcr[2] option 0 option 1 option 2 option 3 gpio[2] dcu_r2 emiosa[20] ? fp21 siul dcu pwm/timer ? i/o m1 none, none 137 167 pa[3] pcr[3] option 0 option 1 option 2 option 3 gpio[3] dcu_r3 emiosa[19] ? fp20 siul dcu pwm/timer ? i/o m1 none, none 138 168 pa[4] pcr[4] option 0 option 1 option 2 option 3 gpio[4] dcu_r4 emiosa[18] ? fp19 siul dcu pwm/timer ? i/o m1 none, none 139 169 pa[5] pcr[5] option 0 option 1 option 2 option 3 gpio[5] dcu_r5 emiosa[17] ? fp18 siul dcu pwm/timer ? i/o m1 none, none 140 172 pa[6] pcr[6] option 0 option 1 option 2 option 3 gpio[6] dcu_r6 emiosa[15] ? fp17 siul dcu pwm/timer ? i/o m1 none, none 141 173 pa[7] pcr[7] option 0 option 1 option 2 option 3 gpio[7] dcu_r7 emiosa[16] ? fp16 siul dcu pwm/timer ? i/o m1 none, none 142 174
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 35 pa[8] pcr[8] option 0 option 1 option 2 option 3 gpio[8] dcu_g0 emiosb[23] scl_2 fp15 siul dcu pwm/timer i 2 c_2 i/o m1 none, none 143 175 pa[9] pcr[9] option 0 option 1 option 2 option 3 gpio[9] dcu_g1 emiosb[18] sda_2 fp14 siul dcu pwm/timer i 2 c_2 i/o m1 none, none 144 176 pa[10] pcr[10] option 0 option 1 option 2 option 3 gpio[10] dcu_g2 emiosb[20] ? fp13 siul dcu pwm/timer ? i/o m1 none, none 11 pa[11] pcr[11] option 0 option 1 option 2 option 3 gpio[11] dcu_g3 emiosa[13] ? fp12 siul dcu pwm/timer ? i/o m1 none, none 22 pa[12] pcr[12] option 0 option 1 option 2 option 3 gpio[12] dcu_g4 emiosa[12] ? fp11 siul dcu pwm/timer ? i/o m1 none, none 33 pa[13] pcr[13] option 0 option 1 option 2 option 3 gpio[13] dcu_g5 emiosa[11] ? fp10 siul dcu pwm/timer ? i/o m1 none, none 44 pa[14] pcr[14] option 0 option 1 option 2 option 3 gpio[14] dcu_g6 emiosa[10] ? fp9 siul dcu pwm/timer ? i/o m2 none, none 55 pa[15] pcr[15] option 0 option 1 option 2 option 3 gpio[15] dcu_g7 emiosa[9] ? fp8 siul dcu pwm/timer ? i/o m1 none, none 66 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
PXD10 microcontroller data sheet, rev. 1 pinout and signal descriptions freescale semiconductor 36 pb[0] pcr[16] option 0 option 1 option 2 option 3 gpio[16] cantx_0 pdi1 ? ?siul flexcan_0 pdi ? i/o m1 none, none 106 130 pb[1] pcr[17] option 0 option 1 option 2 option3 gpio[17] canrx_0 pdi0 ? ?siul flexcan_0 pdi ? i/o s none, none 105 129 pb[2] pcr[18] option 0 option 1 option 2 option3 gpio[18] txd_0 ? ? ?siul linflex_0 ? ? i/o s none, none 112 140 pb[3] pcr[19] option 0 option 1 option 2 option3 gpio[19] rxd_0 ? ? ?siul linflex_0 ? ? i/o s none, none 111 139 pb[4] pcr[20] option 0 option 1 option 2 option 3 gpio[20] sck_1 ma0 ? ?siul dspi_1 adc ? i/o m1 none, none 48 62 pb[5] pcr[21] option 0 option 1 option 2 option 3 gpio[21] sout_1 ma1 fabm ?siul dspi_1 adc control i/o m1 input, pulldown 49 63 pb[6] pcr[22] option 0 option 1 option 2 option 3 gpio[22] sin_1 ma2 abs[0] ?siul dspi_1 adc control i/o s input, pullup 50 66 pb[7] pcr[23] option 0 option 1 option 2 option 3 gpio[23] sin_0 emiosb[22] ? ?siul dspi_0 pwm/timer ? i/o s none, none 46 56 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 37 pb[8] pcr[24] option 0 option 1 option 2 option 3 gpio[24] sout_0 emiosb[21] ? ?siul dspi_0 pwm/timer ? i/o m1 none, none 45 55 pb[9] pcr[25] option 0 option 1 option 2 option 3 gpio[25] sck_0 emiosb[20] ? ?siul dspi_0 pwm/timer ? i/o m1 none, none 44 54 pb[10] pcr[26] option 0 option 1 option 2 option 3 gpio[26] canrx_1 pdi2 emiosa[23] ?siul flexcan_1 pdi pwm/timer i/o s none, none 107 131 pb[11] pcr[27] option 0 option 1 option 2 option 3 gpio[27] cantx_1 pdi3 emiosa[16] ?siul flexcan_1 pdi pwm/timer i/o m1 none, none 108 132 pb[12] pcr[28] option 0 option 1 option 2 option 3 gpio[28] rxd_1 emiosb[19] pcs2_0 ?siul linflex_1 pwm/timer dspi_0 i/o s none, none 40 48 pb[13] pcr[29] option 0 option 1 option 2 option 3 gpio[29] txd_1 emiosb[18] pcs1_0 ?siul linflex_1 pwm/timer dspi_0 i/o s none, none 41 49 pb[14] ? ? reserved ? ? ? ? ? ? ? pb[15] ? ? reserved ? ? ? ? ? ? ? pc[0] pcr[30] option 0 option 1 option 2 option 3 gpio[30] ? ? ? ans[0] siul ? ? ? i/o j none, none 72 88 pc[1] pcr[31] option 0 option 1 option 2 option 3 gpio[31] ? ? ? ans[1] siul ? ? ? i/o j none, none 71 87 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
PXD10 microcontroller data sheet, rev. 1 pinout and signal descriptions freescale semiconductor 38 pc[2] pcr[32] option 0 option 1 option 2 option 3 gpio[32] ? ? ? ans[2] siul ? ? ? i/o j none, none 70 86 pc[3] pcr[33] option 0 option 1 option 2 option 3 gpio[33] ? ? ? ans[3] siul ? ? ? i/o j none, none 69 85 pc[4] pcr[34] option 0 option 1 option 2 option 3 gpio[34] ? ? ? ans[4] siul ? ? ? i/o j none, none 68 84 pc[5] pcr[35] option 0 option 1 option 2 option 3 gpio[35] ? ? ? ans[5] siul ? ? ? i/o j none, none 67 83 pc[6] pcr[36] option 0 option 1 option 2 option 3 gpio[36] ? ? ? ans[6] siul ? ? ? i/o j none, none 66 82 pc[7] pcr[37] option 0 option 1 option 2 option 3 gpio[37] ? ? ? ans[7] siul ? ? ? i/o j none, none 65 81 pc[8] pcr[38] option 0 option 1 option 2 option 3 gpio[38] ? ? ? ans[8] siul ? ? ? i/o j none, none 62 78 pc[9] pcr[39] option 0 option 1 option 2 option 3 gpio[39] ? ? ? ans[9] siul ? ? ? i/o j none, none 61 77 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 39 pc[10] pcr[40] option 0 option 1 option 2 option 3 gpio[40] ? sound ? ans[10] siul ? sgl ? i/o j none, none 60 76 pc[11] pcr[41] option 0 option 1 option 2 option 3 gpio[41] ? ma0 pcs2_1 ans[11] siul ? adc dspi_1 i/o j none, none 59 75 pc[12] pcr[42] option 0 option 1 option 2 option 3 gpio[42] ? ma1 pcs1_1 ans[12] siul ? adc dspi_1 i/o j none, none 58 74 pc[13] pcr[43] option 0 option 1 option 2 option 3 gpio[43] ? ma2 pcs0_1 ans[13] siul ? adc dspi_1 i/o j none, none 57 73 pc[14] pcr[44] option 0 option 1 option 2 option 3 gpio[44] ? ? ? ans[14] extal32 siul ? ? ? i/o j none, none 56 72 pc[15] pcr[45] option 0 option 1 option 2 option 3 gpio[45] ? ? ? ans[15] xtal32 siul ? ? ? i/o j none, none 55 71 pd[0] pcr[46] option 0 option 1 option 2 option 3 gpio[46] m0c0m ssd0_0 emiosb[23] ?siul smc ssd pwm/timer i/o smd none, none 73 89 pd[1] pcr[47] option 0 option 1 option 2 option 3 gpio[47] m0c0p ssd0_1 emiosb[22] ?siul smc ssd pwm/timer i/o smd none, none 74 90 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
PXD10 microcontroller data sheet, rev. 1 pinout and signal descriptions freescale semiconductor 40 pd[2] pcr[48] option 0 option 1 option 2 option 3 gpio[48] m0c1m ssd0_2 emiosb[21] ?siul smc ssd pwm/timer i/o smd none, none 75 91 pd[3] pcr[49] option 0 option 1 option 2 option 3 gpio[49] m0c1p ssd0_3 emiosb[20] ?siul smc ssd pwm/timer i/o smd none, none 76 92 pd[4] pcr[50] option 0 option 1 option 2 option 3 gpio[50] m1c0m ssd1_0 emiosb[19] ?siul smc ssd pwm/timer i/o smd none, none 79 95 pd[5] pcr[51] option 0 option 1 option 2 option 3 gpio[51] m1c0p ssd1_1 emiosb[18] ?siul smc ssd pwm/timer i/o smd none, none 80 96 pd[6] pcr[52] option 0 option 1 option 2 option 3 gpio[52] m1c1m ssd1_2 emiosb[17] ?siul smc ssd pwm/timer i/o smd none, none 81 97 pd[7] pcr[53] option 0 option 1 option 2 option 3 gpio[53] m1c1p ssd1_3 emiosb[16] ?siul smc ssd pwm/timer i/o smd none, none 82 98 pd[8] pcr[54] option 0 option 1 option 2 option 3 gpio[54] m2c0m ssd2_0 ? ?siul smc ssd ? i/o smd none, none 83 99 pd[9] pcr[55] option 0 option 1 option 2 option 3 gpio[55] m2c0p ssd2_1 ? ?siul smc ssd ? i/o smd none, none 84 100 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 41 pd[10] pcr[56] option 0 option 1 option 2 option 3 gpio[56] m2c1m ssd2_2 ? ?siul smc ssd ? i/o smd none, none 85 101 pd[11] pcr[57] option 0 option 1 option 2 option 3 gpio[57] m2c1p ssd2_3 ? ?siul smc ssd ? i/o smd none, none 86 102 pd[12] pcr[58] option 0 option 1 option 2 option 3 gpio[58] m3c0m ssd3_0 ? ?siul smc ssd ? i/o smd none, none 89 105 pd[13] pcr[59] option 0 option 1 option 2 option 3 gpio[59] m3c0p ssd3_1 ? ?siul smc ssd ? i/o smd none, none 90 106 pd[14] pcr[60] option 0 option 1 option 2 option 3 gpio[60] m3c1m ssd3_2 ? ?siul smc ssd ? i/o smd none, none 91 107 pd[15] pcr[61] option 0 option 1 option 2 option 3 gpio[61] m3c1p ssd3_3 ? ?siul smc ssd ? i/o smd none, none 92 108 pe[0] pcr[62] option 0 option 1 option 2 option 3 gpio[62] m4c0m ssd4_0 emiosa[15] ?siul smc ssd pwm/timer i/o smd none, none 93 109 pe[1] pcr[63] option 0 option 1 option 2 option 3 gpio[63] m4c0p ssd4_1 emiosa[14] ?siul smc ssd pwm/timer i/o smd none, none 94 110 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
PXD10 microcontroller data sheet, rev. 1 pinout and signal descriptions freescale semiconductor 42 pe[2] pcr[64] option 0 option 1 option 2 option 3 gpio[64] m4c1m ssd4_2 emiosa[13] ?siul smc ssd pwm/timer i/o smd none, none 95 111 pe[3] pcr[65] option 0 option 1 option 2 option 3 gpio[65] m4c1p ssd4_3 emiosa[12] ?siul smc ssd pwm/timer i/o smd none, none 96 112 pe[4] pcr[66] option 0 option 1 option 2 option 3 gpio[66] m5c0m ssd5_0 emiosa[11] ?siul smc ssd pwm/timer i/o smd none, none 99 115 pe[5] pcr[67] option 0 option 1 option 2 option 3 gpio[67] m5c0p ssd5_1 emiosa[10] ?siul smc ssd pwm/timer i/o smd none, none 100 116 pe[6] pcr[68] option 0 option 1 option 2 option 3 gpio[68] m5c1m ssd5_2 emiosa[9] ?siul smc ssd pwm/timer i/o smd none, none 101 117 pe[7] pcr[69] option 0 option 1 option 2 option 3 gpio[69] m5c1p ssd5_3 emiosa[8] ?siul smc ssd pwm/timer i/o smd none, none 102 118 pe[8] ? ? reserved ? ? ? ? ? ? ? pe[9] ? ? reserved ? ? ? ? ? ? ? pe[10] ? ? reserved ? ? ? ? ? ? ? pe[11] ? ? reserved ? ? ? ? ? ? ? pe[12] ? ? reserved ? ? ? ? ? ? ? pe[13] ? ? reserved ? ? ? ? ? ? ? pe[14] ? ? reserved ? ? ? ? ? ? ? pe[15] ? ? reserved ? ? ? ? ? ? ? table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 43 pf[0] pcr[70] option 0 option 1 option 2 option 3 gpio[70] emiosa[13] pdi4 emiosa[22] fp39 siul pwm/timer pdi pwm/timer i/o s none, none 113 143 pf[1] pcr[71] option 0 option 1 option 2 option 3 gpio[71] emiosa[12] pdi5 emiosa[21] fp38 siul pwm/timer pdi pwm/timer i/o s none, none 114 144 pf[2] pcr[72] option 0 option 1 option 2 option 3 gpio[72] nmi ? ? ?siul nmi ? ? i/o s none, none 37 45 pf[3] pcr[73] option 0 option 1 option 2 option 3 gpio[73] emiosa[11] pdi6 ? fp37 siul pwm/timer pdi ? i/o m1 none, none 115 145 pf[4] pcr[74] option 0 option 1 option 2 option 3 gpio[74] emiosa[10] pdi7 ? fp36 siul pwm/timer pdi ? i/o m1 none, none 116 146 pf[5] pcr[75] option 0 option 1 option 2 option 3 gpio[75] emiosa[9] dcu_tag ? fp35 siul pwm/timer dcu ? i/o m1 none, none 117 147 pf[6] pcr[76] option 0 option 1 option 2 option 3 gpio[76] sda_0 ? ? fp34 siul i 2 c_0 ? ? i/o s none, none 120 150 pf[7] pcr[77] option 0 option 1 option 2 option 3 gpio[77] scl_0 pcs2_1 ? fp33 siul i 2 c_0 dspi_1 ? i/o s none, none 121 151 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
PXD10 microcontroller data sheet, rev. 1 pinout and signal descriptions freescale semiconductor 44 pf[8] pcr[78] option 0 option 1 option 2 option 3 gpio[78] sda_1 pcs1_1 rxd_1 fp32 siul i 2 c_1 dspi_1 linflex_1 i/o s none, none 122 152 pf[9] pcr[79] option 0 option 1 option 2 option 3 gpio[79] scl_1 pcs0_1 txd_1 fp31 siul i 2 c_1 dspi_1 linflex_1 i/o s none, none 123 153 pf[10] pcr[80] option 0 option 1 option 2 option 3 gpio[80] emiosa[16] pcs0_2 ? fp29 siul pwm/timer quadspi ? i/o m1 none, none 127 157 pf[11] pcr[81] option 0 option 1 option 2 option 3 gpio[81] emiosb[23] io2/pcs1_2 6 ? fp28 siul pwm/timer quadspi ? i/o m1 none, none 128 158 pf[12] pcr[82] option 0 option 1 option 2 option 3 gpio[82] emiosb[16] io3/pcs2_2 6 ? fp27 siul pwm/timer quadspi ? i/o m1 none, none 129 159 pf[13] pcr[83] option 0 option 1 option 2 option 3 gpio[83] io0/sin_2 6 canrx_1 ? fp26 siul quadspi flexcan_1 ? i/o m1 none, none 130 160 pf[14] pcr[84] option 0 option 1 option 2 option 3 gpio[84] io1/sout_2 6 cantx_1 ? fp25 siul quadspi flexcan_1 ? i/o m1 none, none 131 161 pf[15] pcr[85] option 0 option 1 option 2 option 3 gpio[85] sck_2 ? ? fp24 siul quadspi ? ? i/o f none, none 132 162 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 45 pg[0] pcr[86] option 0 option 1 option 2 option 3 gpio[86] dcu_b0 scl_3 sound fp7 siul dcu i 2 c_3 sgl i/o m2 none, none 99 pg[1] pcr[87] option 0 option 1 option 2 option 3 gpio[87] dcu_b1 sda_3 ? fp6 siul dcu i 2 c_3 ? i/o m1 none, none 10 10 pg[2] pcr[88] option 0 option 1 option 2 option 3 gpio[88] dcu_b2 emiosb[19] ? fp5 siul dcu pwm/timer ? i/o m2 none, none 11 11 pg[3] pcr[89] option 0 option 1 option 2 option 3 gpio[89] dcu_b3 emiosb[21] ? fp4 siul dcu pwm/timer ? i/o m1 none, none 12 12 pg[4] pcr[90] option 0 option 1 option 2 option 3 gpio[90] dcu_b4 emiosb[17] ? fp3 siul dcu pwm/timer ? i/o m2 none, none 13 13 pg[5] pcr[91] option 0 option 1 option 2 option 3 gpio[91] dcu_b5 emiosa[8] ? fp2 siul dcu pwm/timer ? i/o m1 none, none 14 14 pg[6] pcr[92] option 0 option 1 option 2 option 3 gpio[92] dcu_b6 ? ? fp1 siul dcu ? ? i/o m2 none, none 15 15 pg[7] pcr[93] option 0 option 1 option 2 option 3 gpio[93] dcu_b7 ? ? fp0 siul dcu ? ? i/o m1 none, none 16 16 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
PXD10 microcontroller data sheet, rev. 1 pinout and signal descriptions freescale semiconductor 46 pg[8] pcr[94] option 0 option 1 option 2 option 3 gpio[94] dcu_vsync ? ? bp0 siul dcu ? ? i/o m2 input, none 17 17 pg[9] pcr[95] option 0 option 1 option 2 option 3 gpio[95] dcu_hsync ? ? bp1 siul dcu ? ? i/o m1 input, none 18 18 pg[10] pcr[96] option 0 option 1 option 2 option 3 gpio[96] dcu_de ? ? bp2 siul dcu ? ? i/o m2 none, none 19 19 pg[11] pcr[97] option 0 option 1 option 2 option 3 gpio[97] dcu_pclk ? ? bp3 siul dcu ? ? i/o m1 none, none 20 20 pg[12] pcr[98] option 0 option 1 option 2 option 3 gpio[98] emiosa[23] sound emiosa[8] fp30 siul pwm/timer sgl pwm/timer i/o s none, none 126 156 pg[13] ? ? reserved ? ? ? ? ? ? ? pg[14] ? ? reserved ? ? ? ? ? ? ? pg[15] ? ? reserved ? ? ? ? ? ? ? ph[0] 7 pcr[99] option 0 option 1 option 2 option 3 gpio[99] tck ? ? ?siul jtag ? ? i/o s input, pullup 36 43 ph[1] 7 pcr[100] option 0 option 1 option 2 option 3 gpio[100] tdi ? ? ?siul jtag ? ? i/o s input, pullup 33 36 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 47 ph[2] 7 pcr[101] option 0 option 1 option 2 option 3 gpio[101] tdo ? ? ?siul jtag ? ? i/o m1 output, none 34 39 ph[3] 7 pcr[102] option 0 option 1 option 2 option 3 gpio[102] tms ? ? ?siul jtag ? ? i/o s input, pullup 35 41 ph[4] pcr[103] option 0 option 1 option 2 option 3 gpio[103] pcs0_0 emiosb[16] clkout ?siul dspi_0 pwm/timer control i/o f none, none 47 61 ph[5] pcr[104] option 0 option 1 option 2 option 3 gpio[104] vlcd 8 ? ? ?siul lcd ? ? i/o s none, none 21 21 ph[6] ? ? reserved ? ? ? ? ? ? ? ph[7] ? ? reserved ? ? ? ? ? ? ? ph[8] ? ? reserved ? ? ? ? ? ? ? ph[9] ? ? reserved ? ? ? ? ? ? ? ph[10] ? ? reserved ? ? ? ? ? ? ? ph[11] ? ? reserved ? ? ? ? ? ? ? ph[12] ? ? reserved ? ? ? ? ? ? ? ph[13] ? ? reserved ? ? ? ? ? ? ? ph[14] ? ? reserved ? ? ? ? ? ? ? ph[15] ? ? reserved ? ? ? ? ? ? ? pj[0] pcr[105] option 0 option 1 option 2 option 3 gpio[105] pdi_de ? ? ?siul pdi ? ? i/o s none, none ?119 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
PXD10 microcontroller data sheet, rev. 1 pinout and signal descriptions freescale semiconductor 48 pj[1] pcr[106] option 0 option 1 option 2 option 3 gpio[106] pdi_hsync ? ? ?siul pdi ? ? i/o s none, none ?120 pj[2] pcr[107] option 0 option 1 option 2 option 3 gpio[107] pdi_vsync ? ? ?siul pdi ? ? i/o s none, none ?121 pj[3] pcr[108] option 0 option 1 option 2 option 3 gpio[108] pdi_pclk ? ? ?siul pdi ? ? i/o m1 none, none ?122 pj[4] pcr[109] option 0 option 1 option 2 option 3 gpio[109] pdi[0] canrx_0 ? ?siul pdi flexcan_0 ? i/o s none, none ?57 pj[5] pcr[110] option 0 option 1 option 2 option 3 gpio[110] pdi[1] cantx_0 ? ?siul pdi flexcan_0 ? i/o m1 none, none ?58 pj[6] pcr[111] option 0 option 1 option 2 option 3 gpio[111] pdi[2] canrx_1 emiosa[22] ?siul pdi flexcan_1 pwm/timer i/o s none, none ?59 pj[7] pcr[112] option 0 option 1 option 2 option 3 gpio[112] pdi[3] cantx_1 emiosa[21] ?siul pdi flexcan_1 pwm/timer i/o m1 none, none ?60 pj[8] pcr[113] option 0 option 1 option 2 option 3 gpio[113] pdi[4] ? ? ?siul pdi ? ? i/o s none, none ?125 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 49 pj[9] pcr[114] option 0 option 1 option 2 option 3 gpio[114] pdi[5] ? ? ?siul pdi ? ? i/o s none, none ?126 pj[10] pcr[115] option 0 option 1 option 2 option 3 gpio[115] pdi[6] ? ? ?siul pdi ? ? i/o s none, none ?127 pj[11] pcr[116] option 0 option 1 option 2 option 3 gpio[116] pdi[7] ? ? ?siul pdi ? ? i/o s none, none ?128 pj[12] pcr[117] option 0 option 1 option 2 option 3 gpio[117] pdi[8] emiosb[17] ? ?siul pdi pwm/timer ? i/o m1 none, none ?135 pj[13] pcr[118] option 0 option 1 option 2 option 3 gpio[118] pdi[9] emiosb[20] ? ?siul pdi pwm/timer ? i/o m1 none, none ?136 pj[14] pcr[119] option 0 option 1 option 2 option 3 gpio[119] pdi[10] emiosa[20] ? ?siul pdi pwm/timer ? i/o m1 none, none ?137 pj[15] pcr[120] option 0 option 1 option 2 option 3 gpio[120] pdi[11] emiosa[19] ? ?siul pdi pwm/timer ? i/o m1 none, none ?138 pk[0] pcr[121] option 0 option 1 option 2 option 3 gpio[121] pdi[12] emiosa[18] dcu_tag ?siul pdi pwm/timer dcu i/o m1 none, none ?141 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
PXD10 microcontroller data sheet, rev. 1 pinout and signal descriptions freescale semiconductor 50 pk[1] pcr[122] option 0 option 1 option 2 option 3 gpio[122] pdi[13] emiosa[17] ? ?siul pdi pwm/timer ? i/o m1 none, none ?142 pk[2] pcr[123] option 0 option 1 option 2 option 3 gpio[123] mcko pdi[10] ? ?siul nexus pdi ? i/o f none, none ?33 pk[3] pcr[124] option 0 option 1 option 2 option 3 gpio[124] mseo pdi[11] ? ?siul nexus pdi ? i/o m1 none, none ?34 pk[4] pcr[125] option 0 option 1 option 2 option 3 gpio[125] evto pdi[12] ? ?siul nexus pdi ? i/o m1 none, none ?35 pk[5] pcr[126] option 0 option 1 option 2 option 3 gpio[126] evti pdi[13] ? ?siul nexus pdi ? i/o m1 none, none ?37 pk[6] pcr[127] option 0 option 1 option 2 option 3 gpio[127] mdo0 pdi[14] ? ?siul nexus pdi ? i/o m1 none, none ?38 pk[7] pcr[128] option 0 option 1 option 2 option 3 gpio[128] mdo1 pdi[15] ? ?siul nexus pdi ? i/o m1 none, none ?40 pk[8] pcr[129] option 0 option 1 option 2 option 3 gpio[129] mdo2 pdi[16] ? ?siul nexus pdi ? i/o m1 none, none ?42 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 51 pk[9] pcr[130] option 0 option 1 option 2 option 3 gpio[130] mdo3 pdi[17] ? ?siul nexus pdi ? i/o m1 none, none ?44 pk[10] pcr[131] option 0 option 1 option 2 option 3 gpio[131] sda_1 emiosa[15] ? ?siul i 2 c_1 pwm/timer ? i/o s none, none ?52 pk[11] pcr[132] option 0 option 1 option 2 option 3 gpio[132] scl_1 emiosa[14] ? ?siul i 2 c_1 pwm/timer ? i/o s none, none ?53 pk[12] ? ? reserved ? ? ? ? ? ? ? pk[13] ? ? reserved ? ? ? ? ? ? ? pk[14] ? ? reserved ? ? ? ? ? ? ? pk[15] ? ? reserved ? ? ? ? ? ? ? notes: 1 alternate functions are chosen by setting the values of the pcr[ n ].pa bitfields inside the siul module. pcr[ n ].pa = 00 ? option 0; pcr[n n .pa = 01 ? option 1; pcr[ n ].pa = 10 ? option 2; pcr[ n ].pa = 11 ? option 3. this is intended to select the output functions; to use one of the input functions, the pcr[ n ].ibe bit must be written to ?1?, regard less of the values selected in the pcr[ n ].pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2 special functions are enabled independently from the standard digital pin functions. enabling standard i/o functions in the pcr registers may interfere with their functionality. adc functions are enabled using the pcr[apc] bit; other functions are enabled by enabling the respective m odule. 3 using the psmi registers in the sy stem integration unit lite (siul), different pads can be multiplexed to the same peripheral i nput. please see the siul chapter of the PXD10 microcontroller reference manual for details. 4 see ta bl e 7 . 5 reset configuration is given as i/o direction and pull, e.g., ?input, pullup?. 6 this option on this pin has alternate functi ons that depend on whether the quadspi is in spi mode or in serial flash mode (sfm) . 7 out of reset pins ph[0:3] are available as jtag pins (tck, tdi, tdo and tms respectively). it is up to the user to configure pi ns ph[0:3] when needed. 8 this pin can be used for lcd supply pin vlcd. refer to the volt age supply pin descriptions in the PXD10 data sheet for details. table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 52 2.8.1 signal details table 7. pad type descriptions abbreviation 1 notes: 1 the pad descriptions refer to the differ ent pad configuration register (pcr) type s. refer to the siul chapter in the device reference manual for the features available for each pad type. description f fast (with gpio and digital alternate function) j slow pads with analog muxing (built for adc channels) m1 medium (with gpio and digital alternate function) m2 programmable medium/slow pad (programmed via the slew rate control in the pcr): slew rate disabled: slow driver configuration (ac/dc parameters same as for a slow pad) slew rate enabled: medium driver configuratio n (ac/dc parameters same as for a medium pad) s slow (with gpio and digital alternate function) smd stepper motor driver (with slew rate control) x oscillator table 8. signal details signal peripheral description abs[0] bam alternate boot se lect. gives an option to boot by downloading code via can or lin. ans[0:15] adc inputs used to bring into th e device sensor-based signals for a/d conversion. ans[0:15] connect to atd channels [32:47]. ma[0:2] adc these three control bits are output to enable the selection for an external analog mux for expansion channels. the available 8 multiplexed channels connect to atd channels [64:71]. fabm force alternate boot mode. forces the device to boot from the external bus (can or lin). if not asserted, the device boots up from the lowest flash sector containing a valid boot signature. dcu_de dcu indicates that valid pixels are present. dcu_hsync dcu horizontal sync pulse for tft-lcd display dcu_pclk dcu output pixel clock for tft-lcd display dcu_r[0:7], dcu_g[0:7], dcu_b[0:7] dcu red, green and blue color 8-bit pixel values for tft-lcd displays dcu_tag dcu indicates when a tagged pixel is present in safety mode dcu_vsync dcu vertical sync pulse for tft-lcd display pcs[0..2]_0, pcs[0..2]_1 dspi peripheral chip selects when device is in master mode; not used in slave modes. sck_0, sck_1 dspi spi clock signal?bidirectional
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 53 sin_0, sin_1 dspi spi data input signal sout_0, sout_1 dspi spi data output signal pcs0_2 quadspi peripheral chip select for serial flash mode or chip select 0 for spi master mode io2/pcs1_2 quadspi chip select 1 for spi mast er mode and bidirectional io2 for serial flash mode io3/pcs2_2 quadspi chip select 2 for spi mast er mode and bidirectional io3 for serial flash mode io0/sin_2 quadspi data input signal for spi master and slave modes and bidirectional io0 for serial flash mode io1/sout_2 quadspi data output signal for spi master and slave modes and bidirectional io1 for serial flash mode sck_2 quadspi clock output signal for spi master and serial flash modes and clock input signal for spi slave mode emiosa[8:23], emiosb[16:23] emios enhanced modular input output system. 16+8 channel emios for timed input or output functions. canrx_0, canrx_1 flexcan receive (rx) pins for the can bus transceiver cantx_0, cantx_1 flexcan transmit (tx) pins for the can bus transceiver scl_0, scl_1, scl_2, scl_3 i 2 c bidirectional serial clock compatible with i 2 c specifications sda_0, sda_1, sda_2, sda_3 i 2 c bidirectional serial data compatible with i 2 c specifications tck jtag debug port serial clock as per jtag specifications tdi jtag debug port serial data input port as per jtag standards specifications tdo jtag debug port serial data output port as per jtag standards specifications tms jtag debug port test mode select si gnal for the jtag tap controller state machine and indicates various state transitions for the tap controller in the device bp[0:3] lcd backplane signals from the lcd controlling the backplane reference voltage for the lcd display fp[0:39] lcd frontplane signals for lcd segments evti nexus nexus2+ event input trigger evto nexus nexus2+ event output trigger table 8. signal details (continued) signal peripheral description
pinout and signal descriptions PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 54 mcko nexus output clock for the development tool mdo[0:3] nexus message output port pins that send information bits to the development tools for messages such as branch trace message (btm), ownership trace message (otm), data trace message (dtm). only available in reduced port mode. mseo nexus output pin?indicates the start or end of the variable length message on the mdo pins pdi[0:17] dcu (pdi) video/graphic data in various rgb modes input to the dcu pdi_de dcu (pdi) input signal indicates the va lidity of pixel data on the input pdi data bus. pdi_hsync dcu (pdi) input indicates the timing re ference for the start of each frame line for the pdi input data. pdi_pclk dcu (pdi) input pixel clock from pdi pdi_vsync dcu (pdi) input indicates the timing re ference for the start of a frame for the pdi input data. rxd_0 linflex sci/lin receive data signal?this port is used to download the code for the bam boot sequence. rxd_1 linflex sci/lin receive data signal . input pad for the lin sci module. connects to the internal lin second port. txd_0 linflex sci/lin transmit data signal. this port is used to download the code for the bam boot sequence. txd_1 linflex sci/lin transmit data signal?t ransmit (output) port for the second lin module in the chip sound sgl sound signal to the speaker/buzzer ssd[0:5]_0 ssd[0:5]_1 ssd[0:5]_2 ssd[0:5]_3 ssd bidirectional control of stepper motors using stall detection module m[0:5]c0m m[0:5]c0p m[0:5]c1m m[0:5]c1p smc controls stepper motors in various configuration clkout mc_cgm output clock?it can be select ed from several internal clocks of the device from the clock generation module. table 8. signal details (continued) signal peripheral description
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 55 3 electrical characteristics 3.1 introduction this section contains electrical characteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs ag ainst damage due to high static voltages. however, it is advisable to take precautions to avoid appli cation of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an a ppropriate logic voltage level (v dd or v ss ). this could be done by internal pull up a nd pull down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represen t the characteristics of th e device and its demands on the system. in the tables where the device logic provides signals with their respective timing characteristics, the symbol ?cc? for controller characteristics is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol ?sr? for system requi rement is included in the symbol column. 3.2 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a bette r understanding, the classi fications listed in table 9 are used and the parameters are tagged accordingly in the tabl es where appropriate. note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 9. parameter classifications classification ta g tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 56 3.3 nvusro register portions of the device configuration, such as hi gh voltage supply, oscill ator margin, and watchdog enable/disable after reset are controlled via bit values in the n onvolatile user options (nvusro) register. for a detailed description of the nvusro re gister, please see the chip reference manual. 3.3.1 nvusro[pad3v5v] field description table 10 shows how nvusro[pad3v5v] cont rols the device configuration. the dc electrical characteristics ar e dependent on the pad3v5v bit value. 3.3.2 nvusro[oscillator_margin] field description table 10 shows how nvusro[oscillator_margin] controls the device configuration. the 4?16 mhz fast external crysta l oscillator consumption is de pendent on the oscillator_margin bit value. table 10. pad3v5v field description 1 notes: 1 see the device reference manual for more information on the nvusro register. value 2 2 default manufacturing value before flash initialization is ?1? (3.3 v) description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 11. oscillator_margin field description 1 notes: 1 see the device reference manual for more information on the nvusro register. value 2 2 default manufacturing value before flash initialization is ?1? description 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz)
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 57 3.4 absolute maximum ratings table 12. absolute maximum ratings symbol c parameter conditions value unit min max v dda sr c voltage on vdda pin (adc reference) with respect to ground (v ssa ) ? ? 0.3 6.0 v v ssa sr c voltage on vssa (adc reference) pin with respect to v ss ?v ss ? 0.1 v ss + 0.1 v v ddpll cc c voltage on vddpll (1.2 v pll supply) pin with respect to ground (v sspll ) ?-0.11.4v v sspll sr c voltage on vsspll pin with respect to v ss12 ?v ss12 ? 0.1 v ss12 + 0.1 v v ddr sr c voltage on vddr pin (regulator supply) with respect to ground (v ssr ) ? ? 0.3 6.0 v v ssr sr c voltage on vssr (regulator ground) pin with respect to v ss ?v ss ? 0.1 v ss + 0.1 v v dd12 cc c voltage on vdd12 pin with respect to ground (v ss12 ) ?-0.11.4v v ss12 cc c voltage on vss12 pin with respect to v ss ?v ss ? 0.1 v ss + 0.1 v v dde_a 1 sr c voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) ? ? 0.3 6.0 v v dde_b 1 sr c voltage on vdde_b (i/o supply) pin with respect to ground (v sse_b ) ? ? 0.3 6.0 v v dde_c 1 sr c voltage on vdde_c (i/o supply) pin with respect to ground (v sse_c ) ? ? 0.3 6.0 v v dde_e 1 sr c voltage on vdde_e (i/o supply) pin with respect to ground (v sse_e ) ? ? 0.3 6.0 v v ddma 1 sr c voltage on vddma (stepper motor supply) pin with respect to ground (v ssma ) ? ? 0.3 6.0 v v ddmb 1 v ddmc 1 sr c voltage on vddmb/c (stepper motor supply) pin with respect to ground (v ssmb ) ? ? 0.3 6.0 v v ss 2 sr c i/o supply ground ? 0 0 v v ssosc sr c voltage on vssosc (osc illator ground) pin with respect to v ss ?v ss ? 0.1 v ss + 0.1 v v lcd sr c voltage on vlcd (lcd supply) pin with respect to v ss ?0v dde_a + 0.3 v v in sr c voltage on any gpio pin with respect to ground (v ss ) ? ? 0.3 6.0 v c relative to v dd ? 0.3 v dd + 0.3 3
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 58 note stresses exceeding the recommended ab solute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operationa l sections of this spec ification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 59 3.4.1 recommended operating conditions note maximum slew time for the supplies to ramp up should be 1 second, which is slowest ramp-up time. caution v dde_c and v dda must be the same voltage. v ddmb and v ddmc must be the same voltage. table 13. recommended operating conditions (3.3 v) symbol c parameter conditions value unit min max v dda 1 sr c voltage on vdda pin (adc reference) with respect to ground (v ss ) ?3.03.6v c relative to v dde_c v dd ? 0.1 v dd + 0.1 v ssa sr c voltage on vssa (adc re ference) pin with respect to v ss ?v ss ? 0.1 v ss + 0.1 v v sspll sr c voltage on vsspll pin with respect to v ss12 ?00v v ddr 2 sr c voltage on vddr pin (regulator supply) with respect to ground (v ssr ) ?3.03.6v v ssr sr c voltage on vssr (regulator groun d) pin with respect to v ss12 ?00v v ss12 4 cc c voltage on vss12 pin with respect to v ss ?v ss ? 0.1 v ss + 0.1 v v dd 3,4,5 sr c voltage on vdd pins (vdde_a, vdde_b, vdde_c, vdde_e, vddma, vddmb, vddmc) with respect to ground (v ss ) ?3.03.6v v ss 6 sr c i/o supply ground ? 0 0 v v dde_a sr c voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) ?3.03.6v v dde_b sr c voltage on vdde_b (i/o supply) pin with respect to ground (v sse_b ) ?3.03.6v v dde_c sr c voltage on vdde_c (i/o supply) pin with respect to ground (v sse_c ) ?3.03.6v v dde_e sr c voltage on vdde_e (i/o supply) pin with respect to ground (v sse_e ) ?3.03.6v v ddma sr c voltage on vddma (stepper motor supply) pin with respect to ground (v ssma ) ?3.03.6v v ddmb sr c voltage on vddmb (stepper motor supply) pin with respect to ground (v ssmb ) ?3.03.6v v ddmc sr c voltage on vddmc (stepper motor supply) pin with respect to ground (v ssmc ) ?3.03.6v
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 60 v ssosc sr c voltage on vssosc (oscillator ground) pin with respect to v ss ?00v v lcd sr c voltage on vlcd (lcd supply) pin with respect to v ss ?0v dde_a + 0.3 v tv dd sr c v dd slope to ensure correct power up ? 5 ? 10 ?6 0.25 v/s t a sr c ambient temperature under bias ? ? 40 105 c t j sr c junction temperature under bias ? 40 150 notes: 1 100 nf capacitance needs to be provided between v dda /v ssa pair. 2 at least 10 f capacitance must be connected between v ddr and v ss . this is required because of sharp surge due to external ballast. 3 v dd refers collectively to i/o voltage supplies, i.e., v dde_a , v dde_b , v dde_c , v dde_e , v ddma , v ddmb and v ddmc . 4 100 nf capacitance needs to be provided between each v dd /v ss pair 5 full electrical specification cannot be guaranteed when vo ltage drops below 3.0 v. in particular, adc electrical characteristics and i/o?s dc electrical specification may not be guaranteed. when voltage drops below v lv d h v l device is reset. 6 v ss refers collectively to i/o voltage supply grounds, i.e., v sse_a , v sse_b , v sse_c , v sse_e , v ssma , v ssmb and v ssmc ) unless otherwise noted. table 14. recommended operating conditions (5.0 v) symbol c parameter conditions value unit min max v dda 1 sr c voltage on vdda pin (adc reference) with respect to ground (v ss ) ?4.55.5v c voltage drop 2 3.0 5.5 c relative to v dde_c v dd ? 0.1 v dd + 0.1 v ssa sr c voltage on vssa (adc reference) pin with respect v ss ?v ss ? 0.1 v ss + 0.1 v v sspll sr c voltage on vsspll pin with respect to v ss12 ?00v v ddr 3 sr c voltage on vddr pin (regulator supply) with respect to ground (v ssr ) ?4.55.5v c voltage drop 2 3.0 5.5 c relative to v dd v dd ? 0.1 v dd + 0.1 v ssr sr c voltage on vssr (regulator ground) pin with respect to v ss12 ?00v v ss12 cc c voltage on vss12 pin with respect to v ss ?v ss ? 0.1 v ss + 0.1 v v dd 4,5 sr c voltage on vdd pins (vdde_a, vdde_b, vdde_c, vdde_e, vddma, vddmb, vddmc) with respect to ground (v ss ) voltage drop 2 4.5 5.5 v table 13. recommended operating conditions (3.3 v) (continued) symbol c parameter conditions value unit min max
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 61 note ram data retention is guarant eed with vdd12 not below 1.08 v. v ss 6 sr c i/o supply ground ? 0 0 v v dde_a sr c voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) ?4.55.5v v dde_b sr c voltage on vdde_b (i/o supply) pin with respect to ground (v sse_b ) ?4.55.5v v dde_c 7 sr c voltage on vdde_c (i/o supply) pin with respect to ground (v sse_c ) ?4.55.5v v dde_e sr c voltage on vdde_e (i/o supply) pin with respect to ground (v sse_e ) ?4.55.5v v ddma sr c voltage on vddma (stepper motor supply) pin with respect to ground (v ssma ) ?4.55.5v v ddmb sr c voltage on vddmb (stepper motor supply) pin with respect to ground (v ssmb ) ?4.55.5v v ddmc sr c voltage on vddmc (stepper motor supply) pin with respect to ground (v ssmc ) ?4.55.5v v ssosc sr c voltage on vssosc (oscillator ground) pin with respect to v ss ?00v v lcd sr c voltage on vlcd (lcd supply) pin with respect to v ss ?0v dde_a +0.3 v tv dd sr c v dd slope to ensure correct power up ? 3 ? 10 ?6 0.25 v/s t a sr c ambient temperature under bias ? ? 40 105 c t j sr c junction temperature under bias ? ? 40 150 c notes: 1 100 nf capacitance needs to be provided between v dda /v ssa pair. 2 full functionality cannot be guaranteed when voltage drop s below 4.5 v. in particular, i/o dc and adc electrical characteristics may not be guaranteed below 4.5 v during the voltage drop sequence. 3 10 f capacitance must be connected between v ddr and v ss12 . this is required because of sharp surge due to external ballast. 4 v dd refers collectively to i/o voltage supplies, i.e., v dde_a , v dde_b , v dde_c , v dde_e , v ddma , v ddmb and v ddmc . 5 100 nf capacitance needs to be provided between each v dd /v ss pair 6 v ss refers collectively to i/o voltage supply grounds, i.e., v sse_a , v sse_b , v sse_c , v sse_e , v ssma , v ssmb and v ssmc ) unless otherwise noted. 7 v dde_c should be the same as v dda with a 100 mv variation, i.e., v dde_c = v dda ? 100 mv. table 14. recommended operating conditions (5.0 v) (continued) symbol c parameter conditions value unit min max
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 62 3.4.2 connecting power supply pins: what to do and what not to do ?do: ? have all power/ground supplies co nnected on the board from a st rong supply source rather than weak voltage divider sources unless ther e is ?no io activity? in the section ? meet the supply specifications for max / ty pical operating conditions to guarantee correct operation ? place the decoupling near the supply/gr ound pin pair for emi emissions reduction ? route high-noise supply/ground away from sensitive signals (for example, adc channels must be away from smd supply/motor pads) ? use star routing for the ballast supply from the vddr supply to avoi d ballast startup noise injected to vddr supply of the device ? use lc inductive filtering for adc, osc, and pll supplies if thes e are generated from common board regulators ? do not: ? violate injection current limit per io/all io pins as per specifications ? connect sensitive supplies/ground on noisy su pplies/ground (that is, adc, pll, and osc) ? use smd supply for generation of noise free supply as these are most noisy lines in the system ? connect different vdd pins (connected together inside the device) to different potentials. 3.5 thermal characteristics table 15. lqfp thermal characteristics symbol c parameter conditions value unit 144-pin 176-pin r ? ja cc d thermal resistance, junction-to-ambient natural convection 1 notes: 1 junction-to-ambient thermal resistance determined pe r jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board?1s 50 43 c/w cc four layer board?2s2p 41 35 c/w r ? jma cc d thermal resistance, junction-to-moving-air ambient 2 @ 200 ft./min., single layer board?1s 41 35 c/w cc @ 200 ft./min., four layer board?2s2p 35 30 c/w r ? jb cc d thermal resistance, junction-to-board 2 2 junction-to-board thermal resistance determined pe r jedec jesd51-8. thermal test board meets jedec specification for the specified package. ?2924c/w r ? jctop cc d thermal resistance, junction-to-case (top) 3 ?109c/w ? jt cc d junction-to-package top thermal characterization parameter, natural convection 4 ?22c/w
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 63 3.5.1 general notes for specification s at maximum junction temperature an estimate of the chip junction temperature, t j , can be obtained from equation 1 : t j = t a + (r ? ja ? p d ) eqn. 1 where: t a = ambient temperature for the package (c) r ? ja = junction to ambient thermal resistance (c/w) p d = power dissipation in the package (w) the thermal resistance values used are based on the jedec jesd51 series of standards to provide consistent values for estimations and comparisons. the difference betw een the values determined for the single-layer (1s) board compared to a four-layer boa rd that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal re sistance is not a constant . the thermal resistance depends on the: ? construction of the applicati on board (number of planes) ? effective size of the board which cools the component ? quality of the thermal and elec trical connections to the planes ? power dissipated by adjacent components connect all the ground and powe r balls to the resp ective planes with one via pe r ball. using fewer vias to connect the package to the planes reduces the thermal performance. thinner planes also reduce the thermal performance. when the clearance between the vias le ave the planes virtually disconnected, the thermal performance is also greatly reduced. as a general rule, the value obtaine d on a single-layer board is within the normal range for the tightly packed printed circuit board. the valu e obtained on a board with the intern al planes is usually within the normal range if the application board has: ? one oz. (35 micron nominal thickness) internal planes ? components are well separated ? overall power dissipation on the board is less than 0.02 w/cm 2 the thermal performance of any component depe nds on the power dissipation of the surrounding components. in addition, th e ambient temperature varies widely wi thin the application. for many natural convection and especially closed box applications, the board temperatur e at the perimeter (edge) of the package is approximately the same as the local ai r temperature near the device. specifying the local ambient conditions explicitly as the board temperatur e provides a more precise description of the local ambient conditions that determine the temperature of the device. 3 junction-to-case at the top of the package determi ned using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. 4 thermal characterization parameter indicating the te mperature difference between the package top and the junction temperature per jedec jesd51-2. when greek le tters are not available, the thermal characterization parameter is written as psi-jt.
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 64 at a known board temperature, the junc tion temperature is estimated using equation 2 : t j = t b + (r ? jb ? p d ) eqn. 2 where: t b = board temperature for the package perimeter (c) r ? jb = junction-to-board thermal re sistance (c/w) per jesd51-8s p d = power dissipation in the package (w) when the heat loss from the package case to the air doe s not factor into the calcu lation, an acceptable value for the junction temperature is predictable. ensure th e application board is similar to the thermal test condition, with the component soldered to a board with internal planes. the thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient th ermal resistance: r ? ja = r ? jc + r ? ca eqn. 3 where: r ? ja = junction to ambient thermal resistance (c/w) r ? jc = junction to case thermal resistance (c/w) r ? ca = case to ambient thermal resistance (c/w) r ? jc s device related and is not affect ed by other factors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ? ca . for example, change the air flow around the device, add a heat sink, change the mounti ng arrangement on the printed circui t board, or change the thermal dissipation on the printed circuit board surrounding th e device. this descripti on is most useful for packages with heat sinks wh ere 90% of the heat flow is through the ca se to heat sink to ambient. for most packages, a better model is required. a more accurate two-resistor th ermal model can be constructed fr om the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case ther mal resistance describes when using a heat sink or where a s ubstantial amount of heat is dissipat ed from the top of the package. the junction-to-board thermal resistan ce describes the thermal performanc e when most of the heat is conducted to the printed circuit board. this model can be used to generate si mple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of the devi ce in the application on a prototype board, use the thermal characterization parameter ( ? jt ) to determine the junction temperature by measuring the temperature at the top center of the package case using equation 4 : t j = t t + ( ? jt x p d ) eqn. 4 where: t t = thermocouple temperature on top of the package (c) ? jt = thermal characterizat ion parameter (c/w) p d = power dissipation in the package (w)
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 65 the thermal characterization parameter is measured in compliance with the je sd51-2 specification using a 40-gauge type t thermoc ouple epoxied to the top center of the package case. position the thermocouple so that the thermocouple junction rests on the package. place a smal l amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. place the thermocouple wire flat against the package case to avoid m easurement errors caused by the co oling effects of the thermocouple wire. references: semiconductor equipment and materials international 805 east middlefield rd. mountain view, ca 94043 usa (415) 964-5111 mil-spec and eia/jesd (jedec) spec ifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . 3.6 electromagnetic compatib ility (emc) characteristics susceptibility tests are performed on a sa mple basis during product characterization. 3.6.1 emc requirements on board the following practices help mi nimize noise in applications. ? place a 100 nf capacitor between each of the v dd12 /v ss12 supply pairs and also between the v ddpll /v sspll pair. the voltage regulator also requires stability capacitors fo r these supply pairs. ? place a 10 ? f capacitor on vddr. ? isolate vddr with ballast emitter to a void voltage droop during standby mode exit. ? enable pad slew rate only as necessary to eliminate i/o noise: ? enabling slew rate for smd pa ds will reduce noise on motors. ? disabling slew rate for non-smd pa ds will reduce noise on non-smd ios. ? enable pll modulation ( 2%) for system clock. ? place decoupling capacitors for all hv supplies close to the pins. 3.6.2 designing hardened software to avoid noise problems emc characterization and optimizati on are performed at component le vel with a typical application environment and simplified mcu software. it should be noted th at good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user apply emc software optimi zation and prequali fication tests in relation with the emc level requested for his application. ? software recommendations ?? the software flowchart must incl ude the management of runaway conditions such as:
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 66 ? corrupted program counter ? unexpected reset ? critical data corrupti on (control registers...) ? prequalification trials ?? most of the common failures (une xpected reset and program counter corruption) can be reproduced by manu ally forcing a low state on the re set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be a pplied directly on the device. when unexpected behavior is detected, the software can be ha rdened to prevent unrecoverable errors occurring. 3.6.3 electromagnetic interference (emi) 3.6.4 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using spec ific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 3.6.4.1 electrostatic discharge (esd) electrostatic discharges (a positive th en a negative pulse sepa rated by 1 second) are a pplied to the pins of each sample according to each pin combination. the sa mple size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. table 16. emi testing specifications 1 notes: 1 emi testing and i/o port waveforms per sae j1752/3 issued 1995-03. symbol c parameter conditions value unit min typ max ? sr t scan range 150 khz ? 30 mhz: rbw 9 khz, step size 5 khz 30 mhz ? 1 ghz: rbw 120 khz, step size 80 khz 0.15 ? 1000 mhz ? sr t operating frequency crystal frequency 8 mhz ? 64 ? mhz ? sr t vdd12, vddpll operating voltages ? ? 1.28 ? v ? sr t vdd, vdda operating voltages ??5?v ? sr t maximum amplitude no pll frequency modulation ? 33 ? dbv 2% pll frequency modulation ? 30 ? ? sr t operating temperature ??25?c
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 67 3.6.4.2 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is appl ied to each power supply pin. ? a current injection is applied to eac h input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 3.7 power management electrical characteristics 3.7.1 voltage regulator electrical characteristics the internal high power or main re gulator (hpreg) requires an extern al npn ballast transistor (see table 19 and table 20 ) to be connected as shown in figure 5 as well as an external capacitance (c reg ) to be connected to the device in order to provide a stable low voltage digi tal supply to the device. capacitances should be placed on the boa rd as near as possible to the asso ciated pins. care should also be taken to limit the serial inductance of the board to less than 15 nh. for the PXD10 microcontroller, 100 nf sh ould be placed between each of the v dd12 /v ss12 supply pairs and also between the v ddpll /v sspll pair. these decoupling capacitors are in addition to the required stability capacitance. additionally, 10 ? f should be placed between the v ddr pin and the adjacent v ss pin. v ddr = 3.0 v to 3.6 v / 4.5 v to 5.5 v, t a = ? 40 to 105 c, unless otherwise specified. table 17. esd absolute maximum ratings 1 2 notes: 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for au tomotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and f unctional testing shall be performed per applicable device specification at room temperature followed by ho t temperature, unless specified otherwise in the device specification. symbol c ratings conditions class max value unit v esd(hbm) cc t electrostatic discharge voltage (human body model) t a = 25 c conforming to aec-q100-002 h1c 2000 v v esd(mm) cc t electrostatic discharge voltage (machine model) t a = 25 c conforming to aec-q100-003 m2 200 v esd(cdm) cc t electrostatic discharge voltage (charged device model) t a = 25 c conforming to aec-q100-011 c3a 500 750 (corners) table 18. latch-up results symbol c parameter conditions class lu cc t static latch-up class t a = 105 c conforming to jesd 78 ii level a
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 68 figure 5. external npn ballast connections the capacitor values listed in table 20 include a de-rating factor of 40%, covering toleranc e, temperature, and aging effects. these factors are taken into account to assure proper operation under worst-case conditions. x7r type materials ar e recommended for all capacitors , based on esr characteristics. large capacitors are for regulator stability and should be located near the external ballast transistor. the number of capacitors is not important ? only the overall ca pacitance value and the overall esr value are important. small capacitors are for power supply decoupling, alt hough they do contribute to the overall capacitance values. they should be located close to the device pin. table 19. allowed ballast components part manufacturer recommended derivative bcp68 on, ifx, nxp, fairchild, st, etc. bcp68 bcx68 ifx bcx68-10 bcx68-16 bc817 on, ifx, nxp, fairchild, etc. bc817su bc817-25 bcp56 on, ifx, nxp, fairchild, st, etc. bcp68-10 bcp68-16 table 20. ballast component parameters parameter specification capacitance on vddr 10 ? f (minimum) place close to npn collector stability capacitance on vdd12 40 ? f (minimum) place close to npn emitter decoupling capacitance on vdd12 100 nf ? number of pins (minimum) place on each vdd12/vss12 pair and on the pll supply/ground pair base resistor 20 k ? vrc_ctrl v ddr v dd12 20 k ?
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 69 table 21. voltage regulator electrical characteristics symbol c parameter conditions value unit min typ max t j sr c junction temperature ? ? 40 ? 150 c i reg cc c current consumption reference included, @ 55 c no load @ full load ?? 2 11 ma i l cc c output current capacity dc load current ? ? 200 ma v dd12 cc c output voltage pre-trimming sigma < 7mv ?1.330? v p post-trimming 1.145 1.28 1.32 v sr c external decoupling/stability capacitor 4 capacitances of 10 f each ??10 ? 4f c esr of external cap 0.05 ? 0.2 ? c 1 bond wire r + 1 pad r 0.2 1 ? l bond cc d bonding inductance for bipolar base control pad ? 0?15nh cc d power supply rejection @ dc @ no load c l =10f ? 4?? ? 30 db d @ 200 khz @ no load ? 100 d @ dc @ 200 ma ? 30 d @ 200 khz @ 200 ma ? 30 cc d load current transient c l =10f ? 4 ? ? 10% to 90% of i l (max) in 100 ns t su cc c start-up time after input supply stabilizes 1 notes: 1 time after the input supply to the voltage regulator has ramped up (v ddr ). c l =10f ? 4 ? ? 100 s table 22. low-power voltage regulator electrical characteristics symbol c parameter conditions value unit min typ max t j sr c junction temperature ? ? 40 150 c i reg cc c current consumption reference included, @ 55 c no load @ full load ?? 5 600 ? a i l cc c output current capacity 1 dc load current ? ? 15 ma v dd12 cc c output voltage pre-trimming sigma < 7mv ?1.33 v p post-trimming 1.14 1.24 1.32
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 70 sr c external decoupling/stability capacitor 4 capacitances of 10 f each 10 ? 4?10 ? 4f c esr of external cap 0.1 ? 0.6 ohm c 1 bond wire r + 1 pad r 0.2 ? 1 ohm l bond cc d bonding inductance for bipolar base control pad ? 0?15nh cc d power supply rejection @ dc @ no load c l =10f ? 4??55db d any frequency @ no load 32 d @ dc @ max load 24 d any frequency @ max load 12 cc d load current transient c l =10f ? 4 ? ? 10% to 90% of i l in 10 ? s t su cc c start-up time after input supply stabilizes 2 c l =10f ? 4 ? ? 700 s notes: 1 on this device, the ultra-low-power regulator is always enabled when the low-power regulator is enabled. therefore, the total low-power current capacity is the sum of i l values for the two regulators. 2 time after the input supply to the voltage regulator has ramped up (v ddr ) and the voltage regulator has asserted the power ok signal. table 23. ultra-low-power voltage regulator electrical characteristics symbol c parameter conditions value unit min typ max t j sr c junction temperature ? ? 40 ? 150 c i reg cc c current consumption reference included, @ 55 c no load @ full load ?? 2 100 ? a i l cc c output current capacity dc load current ? ? 5 ma v dd12 cc c output voltage (value @ i l = 0 @ 27 c) pre-trimming sigma < 7mv ?1.33?v post-trimming 1.14 1.24 1.32 table 22. low-power voltage regulator electrical characteristics (continued) symbol c parameter conditions value unit min typ max
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 71 3.7.2 voltage monitor electrical characteristics the device implements a power-on re set (por) module to ensure correc t power-up initializ ation, as well as four low voltage detector s (lvds) to monitor the v dd and the v dd12 voltage while device is supplied: ? por monitors v dd during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd to ensure device reset below minimum functional supply ? lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range ? lvdlvcor monitors power domain no. 1 ? lvdlvbkp monitors power domain no. 0 3.7.3 low voltage domain power consumption table 25 provides dc electrical characteristics for significant appl ication modes. these values are indicative values; actual consum ption depends on the application. cc d power supply rejection @ dc @ no load ? ? 25 db d any frequency @ no load 7 d @ dc @ max load 25 d any frequency @ max load 8 cc d load current transient ? ? 10 to 90 ? a in 70 ? s table 24. low voltage monitor electrical characteristics symbol c parameter conditions 1 notes: 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 105 c, unless otherwise specified value unit min typ max v porh cc p power-on reset threshold ? 1.5 ? 2.6 v v lv d h v3 h cc p lvdhv3 low voltage detector high threshold ? ? ? 2.9 v lv d h v5 h cc p lvdhv5 low voltage detector high threshold ? ? ? 4.4 v lv d h v3 l cc p lvdhv3 low voltage detector low threshold ? 2.6 ? ? v lv d h v5 l cc p lvdhv5 low voltage detector low threshold ? 3.8 ? ? v lv d lv c o r h cc p lvdlvcor low voltage detector high threshold t a = 25 c, after trimming ? ? 1.14 v lv d lv c o r l cc p lvdlvcor low voltage detector low threshold 1.08 ? ? table 23. ultra-low-power voltage regulator electrical characteristics (continued) symbol c parameter conditions value unit min typ max
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 72 table 25. dc electrical characteristics symbol c parameter conditions 1 notes: 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 105 c t a value unit min typ max i ddrun 2 2 value is for maximum peripherals turned on. may vary significantly based on different configurations, active peripherals, operating frequency, etc. cc p run mode current ? ? 130 180 ma i ddhalt cc p halt mode current ? ? 4 25 ma i ddstop cc p stop mode current 16 mhz fa st internal rc oscillator off, hpvreg off 25c ? 250 1800 ? a 105c ? 5 20 ma 16 mhz fast internal rc oscillator off, hpvreg on 25c ? 2.5 6.5 ma 105c ? 7 25 ma i ddstdby cc c standby mode current see ta b l e 2 6 i ddstdby1 3 3 ulpreg on, hp/lpvreg off, 8 kb ram on, device confi gured for minimum consumption, all possible modules switched off. cc p standby1 mode current 25c ? 20 100 ? a 105c ? 180 ? ? a t j = 150c ? ? 350 1500 ? a i ddstdby2 4 4 ulpreg on, hp/lpvreg off, 32 kb ram on, device conf igured for minimum consumption, all possible modules switched off. cc p standby2 mode current 25c ? 30 100 ? a 105c ? 350 ? ? a t j = 150c ? ? 600 2500 ? a table 26. iddstdby specification 1 notes: 1 all current values are typical values. temperature (t a ,c) firc off, 8kb ram on firc on, 8 kb ram on 32 khz sxosc on, 8 kb ram on 32 khz sxosc on, all ram on 3.3v 5.5v 3.3v 5.5v 3.3v 5.5v 3.3v 5.5v ?40 16 ? a25 ? a326 ? a340 ? a16 ? a26 ? a22 ? a32 ? a 018 ? a29 ? a334 ? a347 ? a19 ? a29 ? a26 ? a37 ? a 25 23 ? a33 ? a342 ? a355 ? a24 ? a34 ? a34 ? a45 ? a 55 41 ? a51 ? a363 ? a377 ? a42 ? a53 ? a69 ? a80 ? a 85 93 ? a 104 ? a421 ? a435 ? a100 ? a110 ? a 182 ? a 195 ? a 105 173 ? a 185 ? a502 ? a517 ? a181 ? a194 ? a 344 ? a 358 ? a 125 2 320 ? a 334 ? a648 ? a667 ? a321 ? a335 ? a 620 ? a 638 ? a 150 2 681 ? a 698 ? a 1005 ? a 1028 ? a654 ? a677 ? a1270 ? a1300 ? a
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 73 3.7.4 recommended power-up and power-down order figure 6 shows the recommended order for poweri ng up the power supplies on this device. the 1.2 v regulator output starts after the device?s internal por (vddreg hv) is deasserted at approximately 2.7 v on vddreg. figure 6. recommended order for powering up the power supplies caution the voltages v a and v b in figure 6 must always obey the relation v b ? v a ? 0.7 v. otherwise, currents fr om the 1.2 v supply to the 3.3 v supply may result. figure 7 shows the recommended order for poweri ng down the power suppl ies on this device. it is acceptable for the vdd io hv supply to ramp down faster than the 1.2 v regulator output, even if the latter takes time to discharge the high 40 ? f capacitance. (the capacitor will ultimately discharge.) 2 values provided for reference only. the permitted temp erature range of the chip is specified separately. vddreg hv supply vddreg hv por (internal) 1.2 v regulator output soft startup (approx. 200 ? s) vdd io hv supply (3?5.5 v) ? 2.7 v >= 200 ? s v a v b
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 74 figure 7. recommended order for powering down the power supplies caution the vdd io hv supply must be disa bled after the vddreg hv supply voltage drops below 1.5 v. this is to ensure that the 1.2 v regulator shuts down before the 3.3 v regulator shuts down. 3.7.5 power-up inrush current profile figure 8 shows the power up inrush current profile of the ballast transistor under the worst possible startup condition (fastest pvt and fastest power ramp time). figure 8. power-up inrush current profile vddreg hv supply ? 2.7 v vddreg hv por (internal) 1.2 v regulator output soft startup (approx. 200 ? s) vdd io hv supply (3?5.5 v) > 1.5 v time to discharge 40 ? f capacitance depends on load 1.2 v supply base control current profile 3?5.5 v
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 75 the hpreg has a ?soft startu p? profile which increases the supply in steps of approximately 50 mv in a series of approximately 25 steps. therefore, the peak current is within 750 ma of the maximum current during startup. this elimin ates any noise on the vddr supply during startup and charging of npn emitter stability capacitance of 40 ? f (minimum). soft startup also occurs when waking up from standby mode to limit noise on the vddr supply. in case vddr is shared between the device and the ballast, it must be star routed on the board or isolated as much as possible to avoid any noise injected by the ballast. soft start up will help to limit this noise but a vddr capacitor close to the ballast pin is critical here. a minimum capacitance of 10 ? f is needed. table 27 shows the typical and maximum startup currents. 3.7.6 hpreg load regulation characteristics the hpreg exhibits a very strong load -regulation behavior (t he transition from low- to high-current state is regulated quickly). this is illustrated in figure 10 , which shows a 10?150 ma jump over 10 ns. under any case of load transition, the hpreg res ponds within 100 ns and stabilizes within 5 ? s. this helps improve the stability of the 1.2 v supply and settling time. figure 9. hpreg load regulation 3.8 i/o pad electrical characteristics 3.8.1 i/o pad types the device provides five main i/o pad types: table 27. startup current symbol c parameter value unit typ max i start cc t startup current 300 800 ma 1.2 v supply base control 3 v input supply load
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 76 ? slow pads ? these are the mo st common pads, providing a good co mpromise between transition time and low electromagnetic emission. ? medium pads ? these are provided in two types (m1 and m2) and provide transitions fast enough for the serial communication channels. m2 pads include slew rate control. ? fast pads ? these provide maximum speed. there are used for improved nexus debugging capability. ? smd pads ? these provide a dditional current capability to drive stepper motor loads. ? digital i/o with analog (j) pad ? these provide input and output digital fe atures and analog input for adc. m2 and fast pads can disable slew rate to reduce electromagnetic em ission, at the cost of reducing ac performance. 3.8.2 i/o input dc characteristics table 28 provides input dc el ectrical characteristics as described in figure 10 . figure 10. i/o input dc electrical characteristics definition table 28. i/o input dc electrical characteristics symbol c parameter conditions 1 value unit min typ max v ih sr p input high level cmos schmitt trigger ? 0.65v dd ?v dd + 0.3 v v il sr p input low level cmos schmitt trigger ? ? 0.3 ? 0.35v dd v hys cc d input hysteresis cmos schmitt trigger ? 0.1v dd ?? v il v in v ih pdi = ?1? v dd v hys (gpdi register of siu) pdi = ?0?
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 77 3.8.3 i/o output dc characteristics the following tables provide dc char acteristics for bidirectional pads: ? table 29 provides weak pull figures. both pull-up and pull-down resistances are supported. ? table 30 provides output driver char acteristics for i/o pads wh en in slow configuration. ? table 31 provides output driver charac teristics for i/o pads when in medium configuration (applies to both m1 and m2 type pads). ? table 32 provides output driver char acteristics for i/o pads when in fast configuration. ? table 33 provides smd pad characteristics. i lkg cc p input leakage current ? ?1 ? 1 ? a t a = -40c ? 2 ? na t a = 25c ? 2 ? na ct a = 105c ? 12 500 na pt j = 150c ? 70 1000 na r on cc d resistance of the analog switch inside the j pad type 2 supply range 3.3?5 v ?? 1k ? notes: 1 v dd = 3.3 v ? 10% / 5.0 v ? 10%, t a = ? 40 to 105 c. 2 applies to the j pad type only. table 29. i/o pull-up/pull-down dc electrical characteristics 1 notes: 1 the pull currents are dependent on the hve settings. symbol c parameter conditions 2 2 v dd = 3.3 v ? 10% / 5.0 v ? 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max |i wpu | cc p weak pull-up current absolute value v in = v il , v dd = 5.0v ?? 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 3 3 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. 10 ? 250 pv in = v il , v dd = 3.3v ?? 10% pad3v5v = 1 10 ? 150 |i wpd | cc p weak pull-down current abso- lute value v in = v il , v dd = 5.0v ?? 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 10 ? 250 pv in = v il , v dd = 3.3v ?? 10% pad3v5v = 1 10 ? 150 table 28. i/o input dc electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 78 table 30. slow configuration output buffer electrical characteristics symbol c parameter conditions 1 notes: 1 v dd = 3.3 v ? 10% / 5.0 v ? 10%, t a = ? 40 to 105 c, unless otherwise specified value unit min typ max v oh cc p output high level slow configuration push pull, i oh = ? 2 ma, v dd = 5.0 v ? 10%, pad3v5v = 0 (recommended) 0.8v dd ?? v d push pull, i oh = ? 2 ma, v dd = 5.0 v ? 10%, pad3v5v = 1 2 2 this is a transient c onfiguration during powe r-up. all pads but reset and nexus output (mdox, evto, mck) are configured in input or in high impedance state. 0.8v dd ?? c push pull, i oh = ? 1 ma, v dd = 3.3 v ? 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? v ol cc p output low level slow configuration push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v d push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd c push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr cc t output transition time output pin 3 slow configuration 3 c l calculation should include device and package capacitances (c pkg < 5 pf). c l = 25 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ? ? 50 ns tc l = 50 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ??100 tc l = 100 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ??125 tc l = 25 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ??40 tc l = 50 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ??50 tc l = 100 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ??75 ? i tr50 cc d current slew at c l = 50 pf slow configuration recommended configuration at v dd = 5.0 v ? 10%, pad3v5v = 0 v dd = 3.3 v ? 10%, pad3v5v = 1 ?? 2ma/ns dv dd = 5.0 v ? 10%, pad3v5v = 1 ? ? 7
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 79 table 31. medium configuration output buffer electrical characteristics symbol c parameter conditions 1 notes: 1 v dd = 3.3 v 10% / 5.0 v ? 10%, t a = ? 40 to 105 c, unless otherwise specified value unit min typ max v oh cc p output high level medium configuration push pull, i oh = ? 2 ma, v dd = 5.0 v ? 10%, pad3v5v = 0 (recommended) 0.8v dd ?? v d push pull, i oh = ? 1 ma, v dd = 5.0 v ? 10%, pad3v5v = 1 2 2 this is a transient c onfiguration during powe r-up. all pads but reset and nexus output (mdox, evto, mck) are configured in input or in high impedance state. 0.8v dd ?? c push pull, i oh = ? 1 ma, v dd = 3.3 v ? 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? v ol cc p output low level medium configuration push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v d push pull, i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd c push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr cc t output transition time out- put pin 3 medium configuration 3 c l includes device and package capacitance (c pkg <5 pf). c l = 25 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ? ? 10 ns tc l = 50 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ??20 tc l = 100 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ??40 tc l = 25 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ??12 tc l = 50 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ??25 tc l = 100 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ??40 ? i tr50 cc d current slew at c l = 50 pf medium configuration recommended configuration at v dd = 5.0 v ? 10%, pad3v5v = 0 v dd = 3.3 v ? 10%, pad3v5v = 1 ??7ma/ns dv dd = 5.0 v ? 10%, pad3v5v = 1 ? ? 16
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 80 table 32. fast configuration output buffer electrical characteristics symbol c parameter conditions 1 notes: 1 v dd = 3.3 v ? 10% / 5.0 v ? 10%, t a = ? 40 to 105 c, unless otherwise specified value unit min typ max v oh cc p output high level fast configuration push pull, i oh = ? 14 ma, v dd = 5.0 v ? 10%, pad3v5v = 0 (recommended) 0.8v dd ?? v d push pull, i oh = ? 7 ma, v dd = 5.0 v ? 10%, pad3v5v = 1 2 2 this is a transient c onfiguration during powe r-up. all pads but reset and nexus output (mdox, evto, mck) are configured in input or in high impedance state. 0.8v dd ?? c push pull, i oh = ? 11 ma, v dd = 3.3 v ? 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? v ol cc p output low level fast configuration push pull, i ol = 14 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v d push pull, i ol = 7 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd c push pull, i ol = 11 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr cc t output transition time output pin 3 fast configuration 3 c l includes device and package capacitance (c pkg <5 pf). c l = 25 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ?? 4 ns tc l = 50 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ?? 6 tc l = 100 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ??12 tc l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 4 tc l = 50 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ?? 7 tc l = 100 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ??12 ? i tr50 cc d current slew at c l = 50 pf fast configuration v dd = 5.0 v ? 10%, pad3v5v = 0 (recommended configuration) ??55ma/ns dv dd = 3.3 v ? 10%, pad3v5v = 1 (recommended configuration) ??40 dv dd = 5.0 v ? 10%, pad3v5v = 1 ? ? 100
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 81 3.8.4 i/o pad current specification the i/o pads are distributed across the i/o supply segment. each i/o supply segment is associated to a v dd /v ss supply pair as described in table 34 . table 35 provides i/o consumption figures. in order to ensure device reliabil ity, the average current of the i/o on a single segment should remain below the i av g s e g maximum value. in order to ensure device functiona lity, the sum of the dynamic and stat ic current of the i/o on a single segment should remain below the i dynseg maximum value. table 33. smd pad electrical characteristics symbol c parameter conditions value unit min typ max v il cc p low level input voltage ? ?0.4 ? 0.35 ? v ddm v v ih cc p high level input voltage ? 0.65 ? v ddm ?v ddm +0.4 v hyst cc c schmitt trigger hysteresis ? 0.1 ? v ddm ?? v ol cc p low level output voltage i ol = 20 ma 1 notes: 1 vdd = 5.0 v 10%, tj = -40 to 150 c. ? ? 0.32 i ol = 30 ma 2 2 vdd = 5.0 v 10%, tj = -40 to 130 c. ? ? 0.48 v oh cc p high level output voltage i oh = ?20 ma 1 v ddm ?0.32 ? ? i oh = ?30 ma 2 v ddm ?0.48 ? ? i pu cc p internal pull-up device current v in =v il ?130 ? ? ? a v in =v ih ? ? ?10 i pd cc p internal pull-down device current v in =v il 10 ? ? v in =v ih ? ? 130 i in cc p input leakage current ? -1 ? 1 r dsonh cc c smd pad driver active high impedance ioh ? ?30 ma 2 ??16 ? r dsonl cc c smd pad driver active low impedance iol ? 30 ma 2 ??16 ? v omatch cc p output driver matching v oh /v ol i oh /i ol ? 30 ma 2 ??90mv
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 82 table 34. i/o supply segment package supply segment a 1 notes: 1 lcd pad segment containing pad supplies v dde_a b 2 2 miscellaneous pad segment containing pad supplies v dde_b c 3,4 3 adc pad segment containing pad supplies v dde_c 4 v dde_c should be the same as v dda with a 100 mv variation, i.e., v dde_c = v dda ? 100 mv. d 5 5 stepper motor pad segment containing i/o supplies v ddma , v ddmb , v ddmc e 6 6 miscellaneous pad segment containing pad supplies v dde_e 144 lqfp pins 1?21 pins 113?144 pins 22? 52 pins 53?72 pins 73?102 pins 103?112 176 lqfp pins 1?21 pins 143?176 pins 22?68 pins 69?88 pins 89?118 pins 119?142 table 35. i/o consumption symbol c parameter conditions 1 value unit min typ max i swtslw cc d dynamic i/o current for slow configuration c l = 25 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ??20ma dc l = 25 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ??16 i swtmed cc d dynamic i/o cu rrent for medium configuration c l = 25 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ??29ma dc l = 25 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ??17 i swtfst cc d dynamic i/o current for fast configuration c l = 25 pf, v dd = 5.0 v ? 10%, pad3v5v = 0 ??110ma dc l = 25 pf, v dd = 3.3 v ? 10%, pad3v5v = 1 ??50 i rmsslw cc d root mean square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v ? 10%, pad3v5v = 0 ??2.3ma dc l = 25 pf, 4 mhz v dd = 5.0 v ? 10%, pad3v5v = 0 ??3.2 dc l = 100 pf, 2 mhz v dd = 5.0 v ? 10%, pad3v5v = 0 ??6.6 dc l = 25 pf, 2 mhz v dd = 3.3 v ? 10%, pad3v5v = 1 ??1.6 dc l = 25 pf, 4 mhz v dd = 3.3 v ? 10%, pad3v5v = 1 ??2.3 dc l = 100 pf, 2 mhz v dd = 3.3 v ? 10%, pad3v5v = 1 ??4.7
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 83 i rmsmed cc d root mean square i/o current for medium configuration c l = 25 pf, 2 mhz v dd = 5.0 v ? 10%, pad3v5v = 0 ??6.6ma dc l = 25 pf, 4 mhz v dd = 5.0 v ? 10%, pad3v5v = 0 ??13.4 dc l = 100 pf, 2 mhz v dd = 5.0 v ? 10%, pad3v5v = 0 ??18.3 dc l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??5.0 dc l = 25 pf, 4 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??8.5 dc l = 100 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??11.0 i rmsfst cc d root mean square i/o current for fast configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??22.0ma dc l = 25 pf, 4 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??33.0 dc l = 100 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??56.0 dc l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14.0 dc l = 25 pf, 4 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??20.0 dc l = 100 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??25.0 i dynseg sr d sum of all the dynamic and static i/o current within a supply seg- ment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 110 ma dv dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma dv dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 i ddmxavg sr d sum of currents of two motors assigned to segment v ddmx , v ssmx pair v dd = 5.0 v 10%, pad3v5v = 0 t j =130 ? c ??90 v dd = 5.0 v 10%, pad3v5v = 0 t j =?40 ? c ??120 notes: 1 v dd = 3.3 v ? 10% / 5.0 v ? 10%, t a = ? 40 to 105 c, unless otherwise specified table 35. i/o consumption (continued) symbol c parameter conditions 1 value unit min typ max
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 84 3.9 ssd specifications 3.9.1 electrical characteristics 3.9.2 accumulator values equation 5 describes the accumulator value in unipolar configurat ion. the voltage v in is applied between the integrator input and v ddm . the internal generated reference voltage is not connected. the accumulator value is a function of v ddm , the number of samples (nsample) take n and the ssd constant (ssdconst). the ssd constant and offset (ssdconst, ssd offset) vary with temperature and process. eqn. 5 equation 6 describes the accumulator value in bipolar configura tion. the voltage v in is applied between the integrator input and the reference output. the acc umulator value depends on the same parameters as in the unipolar case but the inaccuracy of the voltage reference (vvref) is compensated. eqn. 6 3.10 reset electrical characteristics table 36. ssd electrical characteristics symbol c parameter value 1 notes: 1 vdd = 5.0v +/- 10%, tj = -40c to +150c. unit min typ max v vref cc p reference voltage (i vref =0) v ddm /2 - 0.02 v ddm /2 v ddm /2 + 0.02 v i vref cc p reference voltage output current 1.85 ? ? ma r in cc d input resistance (against v ddm /2) 0.8 1.0 1.2 m ? v in cc c input common mode range v ssm ?v ddm v ssd const cc c ssd constant 0.549 0.572 0.597 ? ssd offset cc c ssd offset (unipolar, n sample = 256) ?9 ? 9 counts ssd offset (bipolar, n sample = 256) ?8 ? 8 ssd offset (bipolar with offset cancellation, n sample = 256) ?5 ? 5 f ssdsmp cc d ssd cmpout sample rate 0.5 ? 2.0 mhz accval v in vddm ?? 2 ? ? vddm ssdconst ? ---------------------------- ------------------- - nsample ssdoffset + ? = accval v in vddm ssdconst ? ---------------------------- ------------------- - nsample ssdoffset + ? =
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 85 the device implements a de dicated bidirectional reset pin. figure 11. start-up reset requirements figure 12. noise filtering on reset signal v il v dd device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 86 table 37. reset electrical characteristics symbol c parameter conditions 1 notes: 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 105 c, unless otherwise specified value unit min typ max v ih sr p input high level cmos schmitt trigger ?0.65v dd ?v dd + 0.4 v v il sr p input low level cmos schmitt trigger ? ? 0.4 ? 0.35v dd v v hys cc d input hysteresis cmos schmitt trigger ?0.1v dd ??v v ol cc p output low level push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v d push pull, i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 2 this is a transient configuration during power-up, up to the end of reset phase2 (refer to reset generation module (rgm) section of the de vice reference manual). ? ? 0.1v dd c push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr cc t output transition time output pin 3 medium configuration 3 c l includes device and package capacitance (c pkg <5 pf). c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??10ns tc l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??20 tc l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??40 tc l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??12 tc l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??25 tc l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??40 w frst sr p reset input filtered pulse ? ? ? 40 ns w nfrst sr p reset input not filtered pulse ? 1000 ? ? ns i wpu cc p weak pull-up current absolute value ?10?150a d run current during reset before flash is ready ? 10 ? ma after flash is ready ? 20 ? ma
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 87 3.11 fast external crystal o scillator (4?16 mhz) electrical characteristics the device provides an os cillator/resonator driver. figure 13 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. figure 13. crystal oscillator and resonator connection scheme note xtal/extal must not be directly used to drive external circuits. table 38. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance esr ? crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c1 = c2 (pf) 1 shunt capacitance between xtalout and xtalin c0 2 (pf) 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 c l c l crystal extal xtal resonator extal xtal device device device extal xtal i r v dd
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 88 figure 14. fast external crystal oscillator (4?16 mhz) electrical characteristics notes: 1 the values specified for c1 and c2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, et c.) as the ac / transient behavior depends upon them. 2 the value of c0 specified here includes 2 pf additional capacitance for parasitics (to be seen with bond-pads, package, etc.). table 39. resonator description cstcr4m00g53-r0 cstcr4m00g55-r0 vibration fundamental fr (khz) 3929.50 3898.00 fa (khz) 4163.25 4123.00 fa?fr (df) (khz) 233.75 225.00 ra (k ? ) 372.41 465.03 r1 ( ? ) 12.78 11.38 l1 (mh) 0.84443 0.88244 c1 (pf) 1.94268 1.88917 co (pf) 15.85730 15.90537 qm 1630.93 1899.77 cl1 (nominal) (pf) 15 39 cl2 (nominal) (pf) 15 39 v fxoscop t fxoscsu v xtal v fxosc valid internal clock 90% 10% 1/f fxosc s_mtrans bit (me_gs register) ?1? ?0?
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 89 3.12 slow external crystal oscillator (32 khz) electrical characteristics the device provides a low power oscillator/resonator driver. table 40. fast external crystal oscillator (4 to 16 mhz) electrical characteristics symbol c parameter conditions 1 notes: 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 105 c, unless otherwise specified value unit min typ max f fxosc sr ? fast external crystal oscillator frequency ? 4.0 ? 16.0 mhz g mfxosc cc c fast external crystal oscillator transconductance v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 0 2.2 ? 8.2 ma/v cc p v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 0 2.0 ? 7.4 cc c v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 1 2.7 ? 9.7 cc c v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 1 2.5 ? 9.2 v fxosc cc t oscillation amplitude at extal f osc = 4 mhz, oscillator_margin = 0 1.3 ? ? v f osc = 16 mhz, oscillator_margin = 1 1.3 ? ? v fxoscop cc c oscillation operating point ? ? 0.95 ? v i fxosc ,2 2 stated values take into account only analog module cons umption but not the digital contributor (clock tree and enabled peripherals) cc t fast external crystal oscillator consumption ??23ma t fxoscsu cc t fast external crystal oscillator start-up time f osc = 4 mhz, oscillator_margin = 0 ?? 6ms f osc = 16 mhz, oscillator_margin = 1 ??1.8 v ih sr p input high level cmos (schmitt trigger) oscillator bypass mode 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) oscillator bypass mode ? 0.4 ? 0.35v dd v
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 90 figure 15. crystal oscillator and resonator connection scheme note pc[14]/pc[15] must not be directly used to drive external circuits. figure 16. slow external crystal oscillator (32 khz) timing c y c x crystal pc[14] pc[15] resonator pc[14] pc[15] device device oscon bit (osc_ctl register) t sxoscsu ?1? v sxosc_xtal v sxosc valid internal clock 90% 10% 1/f sxosc ?0?
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 91 3.13 fmpll electrical characteristics the device provides a frequency-m odulated phase-locked loop (fmpll) m odule to generate a fast system clock from the main oscillator driver. table 41. slow external crystal oscillator (32 khz) electrical characteristics symbol c parameter conditions 1 notes: 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 105 c, unless otherwise specified value unit min typ max f sxosc sr t slow external crystal oscillator frequency ? 32 ? 40 khz v sxosc cc t oscillation amplitude v dd = 3.3 v 10% 1.12 1.33 1.74 v tv dd = 5.0 v 10% 1.12 1.37 1.74 i sxosc cc d slow external crystal oscillator consumption ???5a t sxoscsu cc t slow external crystal oscillator start-up time ???2 2 2 the quoted figure is based on a board that is properly laid out and has no stray capacitances. s v ih sr d input high level cmos schmitt trigger oscillator bypass mode 0.65v dd ?v dd + 0.4 v v il sr d input low level cmos schmitt trigger oscillator bypass mode ? 0.4 ? 0.35v dd v table 42. fmpll electrical characteristics symbol c parameter conditions 1 notes: 1 v ddpll = 1.2 v 10%, t a = ? 40 to 105 c, unless otherwise specified. value unit min typ max f pllin sr t fmpll reference clock 2 2 pllin clock retrieved directly from fxosc clock. input characteristics are granted when oscillator is used in functional mode. when bypass mode is used, oscillator input clock should verify f pllin and ? pllin . ?4?64mhz ? pllin sr t fmpll reference clock duty cycle 2 ?40?60% f pllout cc t fmpll output clock frequency ? 16 ? 64 mhz f cpu cc t system clock frequency ? ? ? 64 3 3 f cpu 64 mhz can be achieved only at temperatures up to t a = 105 c with a maximum fm depth of 2%. mhz t lock cc t fmpll lock time stable oscillator (f pllin = 16 mhz) ? ? 200 s ? t pkjit cc t fmpll jitter (peak to peak) f pllin = 16 mhz (resonator) ? ? 220 ps ? t ltjit cc t fmpll long term jitter f pllin = 16 mhz (resonator) ? ? 1.5 ns i pll cc d fmpll consumption t a = 25 c ? ? 4 ma
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 92 3.14 fast internal rc oscillator (16 mhz) electrical characteristics the device provides a 16 mhz fast in ternal rc oscillator. this is used as the default clock at the power-up of the device. 3.15 slow internal rc oscillator (128 khz) electrical characteristics the device provides a 128 khz slow internal rc oscillator . this can be us ed as the reference clock for the rtc module. table 43. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions 1 notes: 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 105 c, unless otherwise specified. value unit min typ max f firc cc p fast internal rc oscillator high frequency t a = 25 c, trimmed 16 mhz sr ? ? 12 20 ? fircvar cc c fast internal rc oscillator variation across temperature (t a = -40c to 105c) and supply with respect to f firc at t a = 25 c in high-frequency configuration trimmed ? ? 5?+5% i fircrun cc d fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed ? ? ? 200 a i fircpwd cc d fast internal rc oscillator high frequency current in power down mode t a = 25 c ? ? ? 1 a i fircstop cc d fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off ? 0.3 ? ma d sysclk = 2 mhz ? 2 ? d sysclk = 4 mhz ? 2.5 ? d sysclk = 8 mhz ? 3.3 ? d sysclk = 16 mhz ? 5.2 ? t fircsu cc p fast internal rc oscillator start-up time v dd = 5.0 v 10% ? 1 2 s
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 93 3.16 flash memory electrical characteristics table 44. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions 1 notes: 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 105 c, unless otherwise specified. value unit min typ max f sirc cc p slow internal rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz sr ? ? 100 150 ? sircvar cc c slow internal rc oscillator variation across temperature (t a = -40c to 105c) and supply with respect to f sirc at t a = 25 c in high frequency configuration trimmed -10% +10% khz i sirc cc d slow internal rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a t sircsu cc c slow internal rc oscillator start-up time t a = 25 c, v dd = 5.0 v 10% ? 8 12 s table 45. program and erase specifications symbol c parameter value unit typ 1 notes: 1 typical program and erase times assume nominal supply values and operation at 25 c. initial max 2 2 initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage. max 3 3 the maximum program and erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. t dwprogram cc c double word (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. 22 50 500 s t 16kpperase cc c 16 kb block pre-program and erase time 300 500 5000 ms t 32kpperase cc c 32 kb block pre-program and erase time 400 600 5000 ms t 128kpperase cc c 128 kb block pre-program and erase time 800 1300 7500 ms t eslat cc d erase suspend latency ? 30 30 s
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 94 3.17 adc electrical characteristics the device provides a 10-bit succe ssive approximation register (sar ) analog to digital converter. table 46. flash module life symbol c parameter conditions value unit min typ p/e cc c number of program/erase cycles per block for 16 kb blocks over the operating temperature range (t j ) ? 100000 ? cycles p/e cc c number of program/erase cycles per block for 32 kb blocks over the operating temperature range (t j ) ? 10000 100000 cycles p/e cc c number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) ? 1000 100000 cycles retention cc c minimum data retention at 85 c average ambient temperature 1 notes: 1 ambient temperature averaged over duration of applic ation, not to exceed recommended product operating temperature range. blocks with 0?1,000 p/e cycles 20 ? years blocks with 10,000 p/e cycles 10 ? years blocks with 100,000 p/e cycles 5 ? years table 47. flash memory read access timing symbol c parameter condition 1 notes: 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 ? c, unless otherwise specified max value unit f read cc p maximum frequency for flash memory reading 2 wait states 64 mhz c 1 wait state 40 c 0 wait states 20
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 95 figure 17. adc characteristics and error definitions 3.17.1 input impedance and adc accuracy in the following analysis, the input circuit corr esponding to the precise channels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency character istics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infi nite. this capacito r contributes to attenuating the noise presen t on the input pin; furt hermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. a real filter can typi cally be obtained by using a series resistan ce with a capacitor on the input pin (simple rc filter). the rc filtering may be limited acco rding to the value of source impedance of the transducer (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dda / 1024
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 96 or circuit supplying the anal og signal to be measured. th e filter at the input pins must be designed taking into account the dynamic characteristics of the i nput signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contributor is represente d by the charge sharing effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a re sistive path to ground. fo r instance, assuming a c onversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (f c ? c s ), where f c represents the conversion rate at the considered channel). to mi nimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 7 : eqn. 7 equation 7 generates a constraint for external network de sign, in particular on resistive path. internal switch resistances (r sw and r ad ) can be neglected with resp ect to external resistances. figure 18. input equivalent circuit (precise channels) v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb ? r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 97 figure 19. input equivalent circuit (extended channels) a second aspect involving the capaci tance network shall be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivale nt circuit reported in figure 18 ): a charge sharing phenomenon is installed wh en the sampling phase is started (a/d switch close). figure 20. transient behavior during sampling phase in particular two different transi ent periods can be distinguished: ? a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely di scharged): considering a worst case r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 )
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 98 (since the time constant in real ity would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is eqn. 8 equation 8 can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/ d converter circuitry has been de signed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 9 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 10 : eqn. 10 ? a second charge transfer involves also c f (that is typically bigger th an the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality w ould be faster), the time constant is: eqn. 11 in this case, the time constant depends on the ex ternal circuit: in part icular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 12 of course, r l shall be sized also according to the curr ent limitation constraints, in combination with r s (source impedance) and r f (filter resist ance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be much higher than v a1 . equation 13 must be respected (cha rge balance assuming now c s already charged at v a1 ): eqn. 13 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provi de the extra charge to compensate the voltage drop on c s with respect to the ideal ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ? ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? =t s ? ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? =
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 99 source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing. figure 21. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the filter is greater than or at leas t equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is sele cted (fastest conversi on rate at a specific channel): in conclusion it is evident th at the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equati ons above, it is simple to derive equation 14 between the ideal and real sampled voltage on c s : eqn. 14 from this formula, in the worst case (when v a is maximum, that is for inst ance 5v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 15 f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 ?? f c (nyquist) f f ? f 0 (anti-aliasing filtering condition) t c ?? 2 r f c f (conversion rate vs. filter pole) noise v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ?
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 100 3.17.2 adc conversion characteristics note for input leakage current specification, see table 28 . table 48. adc conversion characteristics symbol c parameter conditions 1 value unit min typ max v ssa sr d voltage on vssa (adc reference) pin with respect to ground (v ss ) 2 ? ? 0.1 ? 0.1 v v dda sr d voltage on vdda pin (adc reference) with respect to ground (v ss ) ?v dd ? 0.1 ? v dd + 0.1 v v ainx sr d analog input voltage 3 ?v ssa ? 0.1 ? v dda + 0.1 v f adc sr d adc analog frequency ? 6 ? 32 mhz t adc_pu sr d adc power up delay ? ? ? 1.5 s t adc_s cc t sample time 4,5 f adc = 32 mhz, adc_conf_sample_input = 17 0.5 ? ? s t f adc = 6 mhz, adc_conf_sample_input = 127 ??21 t adc_c cc t conversion time 6 f adc = 32 mhz, adc_conf_comp = 2 0.625 ? ? s c s cc d adc input sampling capacitance ?? ? 3 pf c p1 cc d adc input pin capacitance 1 ? ?? 3 pf c p2 cc d adc input pin capacitance 2 ??? 1 pf c p3 cc d adc input pin capacitance 3 ??? 1 pf r sw1 cc d internal resistance of analog source ? ? ? 1 k ? r sw2 cc d internal resistance of analog source ??? 1 k ? r ad cc d internal resistance of analog source ??? 0.1 k ? i inj sr t input current injection current injection on one adc input, different from the converted one ? 5? 5 ma inl cc p integral non linearity no overload ? .5 ? 2.5 lsb dnl cc p differential non linearity no overload ? 1.0 ? 1.0 lsb
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 101 3.18 lcd driver electrical characteristics ofs cc t offset error after offset cancellation ? 0.5 ? lsb gne cc t gain error ? 0.6 ? lsb tuex cc p total unadjusted error for extended channel without current injection ?3 ? 3 lsb t with current injection ?4 ? 4 notes: 1 v dda = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 105 c, unless otherwise specified. 2 analog and digital v ss must be common (to be tied together externally). 3 v ainx may exceed v ssa and v dda limits, remaining on absolute maximum ra tings, but the results of the conversion will be clamped respectively to 0x000 or 0x3ff 4 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the c apacitance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc_s depend on programming. 5 the maximum sample rate is 1 million samples per second, provided the source impedance and current limiter(>1 k ? ) are calculated adequately. - filter capacitor at analog source output must meet the criteria cf (filter capacitor) > 2048*cs (sampling capacitor which is 3 pf) 6 this parameter does not include the sample time t adc_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. table 49. lcd driver specifications symbol c parameter value 1 notes: 1 v dd =5.0v10%, t a = ?40?105 c, unless otherwise specified unit min typ max vlcd sr c voltage on vlcd (lcd supply) pin with respect to vss 0 ? vdde + 0.3 v z bp/fp cc t lcd output impedance (bp[n-1:0],fp[m-1:0]) for output levels vlcd, vss 2 2 outputs measured one at a time, low impedance voltage source connected to the vlcd pin. ??5.0k ? i bp/fp cc t lcd output current (bp[n-1:0],fp[m-1:0]) for outputs charge/discharge voltage levels vlcd2/3, vlcd1/2, vlcd1/3) 2 , 3 3 with pwr=10, bsten=0, and bstao=0 ?25? ? a table 48. adc conversion characteristics (continued) symbol c parameter conditions 1 value unit min typ max
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 102 3.19 pad ac specifications table 50. pad ac specifications (5.0 v, pad3v5v = 0) 1 notes: 1 propagation delay from v dd /2 of internal signal to pchannel/nchannel on condition no. pad tswitchon 1 (ns) rise/fall 2 (ns) 2 slope at rising/falling edge frequency (mhz) current slew (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max 1 slow 1.5?30 6 ?50?? 40.04? 2 25 1.5 ? 30 9 ? 100 ? ? 2 0.04 ? 2 50 1.5 ? 30 12 ? 125 ? ? 2 0.04 ? 2 100 1.5 ? 30 16 ? 150 ? ? 2 0.04 ? 2 200 2 medium 1 ? 15 3 ? 10 ? ? 40 2.5 ? 7 25 1 ? 15 5 ? 20 ? ? 20 2.5 ? 7 50 1 ? 15 9 ? 40 ? ? 13 2.5 ? 8 100 1 ? 15 12 ? 70 ? ? 7 2.5 ? 8 200 3 fast 1?6 1?4??10018?55 25 1 ? 6 1.5 ? 6 ? ? 80 18 ? 55 50 1 ? 6 3 ?12??4018?55 100 1 ? 6 5 ?16??2518?55 200 4 pull up/down (5.5 v max) ?????5000?????? 50 parameter classification dcccn/a table 51. pad ac specifications (3.3 v, pad3v5v = 1) 1 no. pad tswitchon 1 (ns) rise/fall 2 (ns) frequency (mhz) current slew (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max 1 slow 3 ? 40 4 ? 40 ? ? 4 0.01 ? 2 25 3 ? 40 6 ? 50 ? ? 2 0.01 ? 2 50 3 ? 40 10 ? 75 ? ? 2 0.01 ? 2 100 3 ? 40 14 ? 100 ? ? 2 0.01 ? 2 200 2 medium 1 ?15 2 ?12??402.5? 7 25 1 ? 15 4 ? 25 ? ? 20 2.5 ? 7 50 1 ? 15 8 ? 40 ? ? 13 2.5 ? 7 100 1 ? 15 14 ? 70 ? ? 7 2.5 ? 7 200
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 103 figure 22. pad output delay 3 fast 1 ? 6 1 ? 4 ??72 3 ?40 25 1?61.5?7??553?40 50 1 ? 6 3 ?12??40 3 ?40 100 1 ? 6 5 ?18??25 3 ?40 200 4 pull up/down (3.6 v max) ?????7500?????? 50 parameter classification dcccn/a notes: 1 propagation delay from v dd /2 of internal signal to pchannel/nchannel on condition 2 slope at rising/falling edge table 51. pad ac specifications (3.3 v, pad3v5v = 1) 1 (continued) no. pad tswitchon 1 (ns) rise/fall 2 (ns) frequency (mhz) current slew (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max v dd /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 104 3.20 ac timing 3.20.1 ieee 1149.1 interface timing table 52. smd pad delays symbol c parameter conditions value unit min typ max ? cc d smd pad delay cl=50pf v dd =5v10% sre=1 ??165ns cl=50pf v dd =5v10% sre=0 ??35 ? cc d smd pad delay cl=50pf v dd =3.3v10% sre=1 ??350 cl=50pf v dd =3.3v10% sre=0 ??50 table 53. jtag interface timing 1 notes: 1 these specifications apply to jtag bounda ry scan only. jtag timing specified at v dd = 3.0 v to 5.5 v, t a = ? 40 to 105 c, and c l = 50 pf with src = 0b11. no. symbol c parameter value unit min max 1t jcyc cc d tck cycle time 100 ? ns 2t jdc cc d tck clock pulse width (measured at v dd /2) 40 60 3t tckrise cc d tck rise and fall times (40%?70%) ? 3 4t tmss, t tdis cc d tms, tdi data setup time 5 ? 5t tmsh, t tdih cc d tms, tdi data hold time 10 ? 6t tdov cc d tck low to tdo data valid ? 40 7t tdoi cc d tck low to tdo data invalid 0 ? 8t tdohz cc d tck low to tdo high impedance ? 30
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 105 figure 23. jtag test clock input timing figure 24. jtag test access port timing tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 106 figure 25. jtag boundary scan timing 3.20.2 nexus debug interface table 54. nexus debug port timing 1 no. symbol c parameter value unit min max 1t mcyc cc d mcko cycle time 22 ? ns 2 ? mdc cc d mcko duty cycle 40 60 % 3t mdov cc d mcko low to mdo data valid 2 ?2 14 ns 4t mseov cc d mcko low to mseo data valid 2 ?2 14 ns 5t evtov cc d mcko low to evto data valid 2 ?2 14 ns 6t evtipw cc d evti pulse width 4 ? t tcyc tck output signals input signals output signals 9 10 11 12 13
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 107 figure 26. nexus output timing figure 27. nexus tck timing 7t evtopw cc d evto pulse width 1 ? t mcyc 8t tcyc cc d tck cycle time 3 100 ? ns 9 ? tdc cc d tck duty cycle 40 60 % 10 t ntdis, t ntmss cc d tdi, tms data setup time 10 ? ns 11 t ntdih, t ntmsh cc d tdi, tms data hold time 5 ? ns 12 t jov cc d tck low to tdo data valid 0 40 ns notes: 1 jtag specifications in this table apply when used for deb ug functionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 3.0 v to 5.5v, t a = ? 40 to 105 c, and c l = 50 pf (c l = 30 pf on mcko), with src = 0b11. 2 mdo, mseo , and evto data is held valid until next mcko low cycle. 3 the system clock frequency needs to be three times faster than the tck frequency. table 54. nexus debug port timing 1 (continued) no. symbol c parameter value unit min max 1 2 4 5 mcko mdo mseo evto output data valid 3 tck 8 9 9
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 108 figure 28. nexus tdi, tms, tdo timing 3.20.3 interface to tft lcd panels figure 29 depicts the lcd interface timing for a generic active matrix color tft panel. in this figure signals are shown with pos itive polarity. the sequen ce of events for active matrix interface timing is: 1. dcu_clk latches data into the pa nel on its positive edge (when positive polarit y is selected). in active mode, dcu_clk runs continuously. 2. dcu_hsync causes the panel to start a new line. it always encompasses at least one pclk pulse. 3. dcu_vsync causes the panel to start a new fram e. it always encompasses at least one hsync pulse. 4. dcu_de acts like an output enable signal to th e lcd panel. this output enables the data to be shifted onto the display. when disabled, the data is invalid and the trace is off. tdo 10 11 tms, tdi 12 tck
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 109 figure 29. tft lcd interface timing overview 1 3.20.3.1 interface to tft lcd panels?pixel level timings figure 30 depicts the horizontal timing (tim ing of one line), including bot h the horizontal sync pulse and data. all parameters shown in the diagram are programmable. this tim ing diagram corres ponds to positive polarity of the dcu_clk signal (meaning the data and sync signals change on the rising edge) and active-high polarity of the dcu_hsync, dcu_vsyn c and dcu_de signals. th e user can select the polarity of the dcu_hsync and dc u_vsync signals via the syn_pol register, whether active-high or active-low. the default is active-high. the dcu_de signal is always active-high. pixel clock inversion and a flexible programmabl e pixel clock delay are also supported. they are programmed via the dcu clock confide register (dccr) in the system clock module. the delta_x and delta_y parameters are prog rammed via the disp_size register. the pw_h, bp_h and fp_h parameters are programmed via th e hsyn para register. the pw_v, bp_v and fp_v parameters are programmed vi a the vsyn_para register. 1. in figure 29 , the ?dcu_ld[23:0]? signal is an aggregation of the dcu?s rgb signals?dc u_r[0:7], dcu_ g[0:7] and dcu_b[0:7]. table 55. lcd interface timing parameters?horizontal and vertical symbol c parameter value unit t pcp cc d display pixel clock period ? ns t pwh cc d hsync pulse width pw_h ? t pcp ns t bph cc d hsync back porch width bp_h ? t pcp ns t fph cc d hsync front porch width fp_h ? t pcp ns t sw cc d screen width delta_x ? t pcp ns t hsp cc d hsync (line) period (pw_h + bp_h + fp_h + delta_x ) ? t pcp ns t pwv cc d vsync pulse width pwv ??? t hsp ns line 1 line 2 line 3 line 4 line n-1 line n dcu_vsync dcu_hsync dcu_hsync dcu_de dcu_clk dcu_ld[23:0] 2 13 m-1m
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 110 figure 30. horizontal sync timing figure 31. vertical sync pulse 3.20.3.2 interface to tft lcd panels t bpv cc d vsync back porch width bp_v ? t hsp ns t fpv cc d vsync front porch width fp_v ? t hsp ns t sh cc d screen height delta_y ? t hsp ns t vsp cc d vsync (frame) period (pw_v + bp_v + fp_v + delta_y ) ? t hsp ns table 55. lcd interface timing parameters?horizontal and vertical (continued) symbol c parameter value unit start of line dcu_clk dcu_ld[23:0] dcu_hsync dcu_de t pwh t bph t hsp t sw t pcp t fph 12 3 delta_x invalid data invalid data start of frame dcu_hsync dcu_ld[23:0] dcu_hsync dcu_de t pwv t bpv t vsp t hcp t fpv 1 2 3 delta_y invalid data invalid data (line data) t sh
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 111 figure 32. tft lcd interface timing parameters 3.20.4 external interrupt (irq) and no n-maskable interrupt (nmi) timing table 56. tft lcd interface timing parameters 1,2,3,4 notes: 1 the characteristics in this table are based on the assumption that data is output at positive edge and displays latch data on negative edge 2 intra bit skew is less than 2 ns 3 load c l = 50 pf for panel frequency up to 20 mhz 4 load c l = 25 pf for panel frequency from 20 to 32 mhz symbol c parameter value unit min typ max t ckp cc d pdi clock period 15.25 ? ? ns ? ck cc d pdi clock duty cycle 40 ? 60 % t dsu cc d pdi data setup time 9.5 ? ? ns t dhd cc d pdi data access hold time 4.5 ? ? ns t csu cc d pdi control signal setup time 9.5 ? ? ns t chd cc d pdi control signal hold time 4.5 ? ? ns cc d tft interface data valid after pixel clock ? ? 6 ns cc d tft interface vsync valid after pixel clock ? ? 5.5 ns cc d tft interface de valid after pixel clock ? ? 5.6 ns cc d tft interface hold time for data and control bits 2 ? ? ns cc d relative skew between the data bits ? ? 3.7 ns dcu_hsync dcu_vsync dcu_de dcu_clk dcu_ld[23:0] t ckh t ckl t chd t csu t dhd t dsu
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 112 figure 33. irq and nmi timing 3.20.5 emios timing table 57. irq and nmi timing no. symbol c parameter value unit min max 1t ipwl cc t irq/nmi pulse width low 200 ? ns 2t ipwh cc t irq/nmi pulse width high 200 ? ns 3t icyc cc t irq/nmi edge to edge time 1 notes: 1 applies when irq/nmi pins are configured for rising edge or falling edge events, but not both. 400 ? ns table 58. emios timing 1 notes: 1 emios timing specified at f sys = 64 mhz, v dd12 = 1.14 v to 1.32 v, vdde_x = 3.0 v to 5.5 v, t a = ? 40 to 105 c, and c l = 50 pf with src = 0b00 no. symbol c parameter value unit min 2 2 there is no limitation on the peripheral for setting the minimum pulse width, the ac tual width is restricted by the pad delays. refer to the pad specification section for the details. max 1t mipw cc d emios input pulse width 4 ? t cyc 2t mopw cc d emios output pulse width 1 ? t cyc 1,2 3 1,2
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 113 3.20.6 flexcan timing the can functions are available as tx pins at normal io pads and as rx pins at the always on domain. there is no filter for the wakeup dominant pulse. any high-to-low edge can caus e wakeup if configured. 3.20.7 deserial serial peripheral interface (dspi) table 59. flexcan timing 1 notes: 1 flexcan timing specified at f sys = 64 mhz, v dd12 = 1.14 v to 1.32 v, vdde_x = 3.0 v to 5.5 v, t a = ? 40 to 105 c, and c l = 50 pf with src = 0b00. no. symbol c parameter value unit min max 1t canov cc d ctnx output valid after clkout rising edge (output delay) ? 22.48 ns 2t cansu cc d cnrx input valid to clkout rising edge (setup time) ? 12.46 ns table 60. dspi timing 1 no. symbol c parameter conditions value unit min max 1t sck ccddspi cycle time 2,3 master (mtfe = 0) slave (mtfe = 0) slave receive only mode 62 62 62 ? ? ? ns ns ns 2t csc cc d pcs to sck delay 4 ?20?ns 3t asc cc d after sck delay 5 ?20?ns 4t sdc cc d sck duty cycle ? 0.4 x t sck 0.6 x t sck ns 5t a cc d slave access time (pcsx active to sout driven) ss active to sout valid ? 40 ns 6t dis cc d slave sout disable time (pcsx inactive to sout high-z or invalid) ss inactive to sout high-z or invalid ? 10 ns 7t pcsc pcsx to pcss time ? 20 ?ns 8t pasc pcss to pcsx time ? 20 ?ns 9t sui cc d data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 6 master (mtfe = 1, cpha = 1) 35 2 20 35 ? ? ? ? ns ns ns ns 10 t hi cc d data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 6 master (mtfe = 1, cpha = 1) ?5 5 10 ?5 ? ? ? ? ns ns ns ns
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 114 figure 34. dspi classic spi timing ? master, cpha = 0 11 t suo cc d data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) ? ? ? ? 14 39 24 15 ns ns ns ns 12 t ho cc d data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) ?3 6 12 ?3 ? ? ? ? ns ns ns ns notes: 1 dspi timing specified at vdde_x = 3.0 v to 5.5 v, t a = ? 40 to 105 c, and c l = 50 pf with src = 0b11. 2 the minimum sck cycle time restricts the baud rate selection for given system clock rate. 3 the actual minimum sck cycle time is limited by pad performance. 4 the maximum value is programmable in dspi_cta rx[pssck] and dspi_ctarx[cssck], program pssck = 2 and cssck = 2 5 the maximum value is programmable in dspi_ctarx[pasc] and dspi_ctarx[asc] 6 this delay value is corresponding to smpl_pt = 00b which is bit field 9 and 8 of dspi_mcr register. table 60. dspi timing 1 (continued) no. symbol c parameter conditions value unit min max data last data first data first data data last data sin sout pcsx sck output 4 7 10 1 9 8 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers in circles refer to values in ta b l e 6 0 .
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 115 figure 35. dspi classic spi timing ? master, cpha = 1 figure 36. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 10 9 8 last data data first data sck output sck output pcsx 7 (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 0 . last data first data 3 4 1 data data sin sout pcsx 4 5 6 7 9 8 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 0 .
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 116 figure 37. dspi classic spi timing ? slave, cpha = 1 figure 38. dspi modified transfer format timing ? master, cpha = 0 5 6 7 10 9 8 last data last data sin sout pcsx first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 0 . pcsx 3 1 4 8 4 7 10 9 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 0 .
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 117 figure 39. dspi modified transfer format timing ? master, cpha = 1 figure 40. dspi modified transfer format timing ? slave, cpha = 0 pcsx 8 7 10 9 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 0 . last data first data 3 4 1 data data sin sout pcsx 4 5 6 7 9 8 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 10 note: numbers in circles refer to values in ta b l e 6 0 .
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 118 figure 41. dspi modified transfer format timing ? slave, cpha = 1 3.20.8 i 2 c timing table 61. i 2 c input timing specifications ? scl and sda no. symbol c parameter value unit min max 1 ? cc d start condition hold time 2 ? ip-bus cycle 1 notes: 1 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device 2 ? cc d clock low time 8 ? ip-bus cycle 1 4 ? cc d data hold time 0.0 ? ns 6 ? cc d clock high time 4 ? ip-bus cycle 1 7 ? cc d data setup time 0.0 ? ns 8 ? cc d start condition setup time (for repeated start condition only) 2 ? ip-bus cycle 1 9 ? cc d stop condition setup time 2 ? ip-bus cycle 1 5 6 7 10 9 8 last data last data sin sout pcsx first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 0 .
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 119 figure 42. i 2 c input/output timing 3.20.9 quadspi timing the following notes apply to table 63 : ? all data are based on a negative edge data launch from PXD10 and a positive edge data capture as shown in the timing diagrams. ? typical values are pr ovided from center-s plit material at 25 ? c and 3.3 v. mini mum and maximum values are from a temperature variation of ?45 ? c to 105 ? c and the following supply conditions: ? io voltage: 3.2 v, core supply: 1.2 v table 62. i 2 c output timing specifications ? scl and sda no. symbol c parameter value unit min max 1 1 notes: 1 programming ibfd (i 2 c bus frequency divider) with the maximum frequency results in the minimum output timings listed. the i 2 c interface is designed to scale the data transition time, moving it to the middle of the scl low period. the actual position is affect ed by the prescale and division values programmed in ifdr. ? cc d start condition hold time 6 ? ip-bus cycle 2 2 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device 2 1 ? cc d clock low time 10 ? ip-bus cycle 1 3 3 3 because scl and sda are open-drain-type outputs, which the processor can only actively drive low, the time scl or sda takes to reach a high level depends on external signal capacitance and pull-up resistor values. ? cc d scl/sda rise time ? 99.6 ns 4 1 ? cc d data hold time 7 ? ip-bus cycle 1 5 1 ? cc d scl/sda fall time ? 99.5 ns 6 1 ? cc d clock high time 10 ? ip-bus cycle 1 7 1 ? cc d data setup time 2 ? ip-bus cycle 1 8 1 ? cc d start condition setup time (for repeated start condition only) 20 ? ip-bus cycle 1 9 1 ? cc d stop condition setup time 10 ? ip-bus cycle 1 scl sda 1 2 3 4 5 6 7 89
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 120 ? io voltage: 3.6 v, core supply: 1.2 v ? all measurements are taken at 70% of vdde levels for clock pin and 50% of vdde level for data pins. ? timings correspond to qspi_smpr = 0x0000_000x. see the PXD10 microcontroller reference manual for details. ? a negative value of hold is an indication of pa d delay on the clock pad (delay between the edge capturing data inside the device a nd the edge appearing at the pin). ? values are with a load of 15pf on the output pins. figure 43. quadspi output timing diagram table 63. quadspi timing symbol c parameter value unit min typ max t cq cc t clock to q delay 1.60 2.4 5.33 ns t s cc t setup time for incoming data 6.1 9.4 12.1 ns t h cc t hold time requirement for incoming data ?12.5 ?8.5 ?7.5 ns t r cc t clock pad rise time 0.4 0.6 1.0 ns t f cc t clock pad fall time 0.3 0.5 0.9 ns sck t cq do 1. last address out 1
electrical characteristics PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 121 figure 44. quadspi input timing diagram the clock profile in figure 45 is measured at 30% to 70% levels of vdde. figure 45. quadspi clock profile t cq sck t h t s do di 1. last address out 2. address captured at flash 3. data out from flash 4. ideal data capture edge 5. delayed data capture ed ge with qspi_smpr=0x0000_000x 6. delayed data capture ed ge with qspi_smpr=0x0000_002x 7. delayed data capture ed ge with qspi_smpr=0x0000_004x 8. delayed data capture ed ge with qspi_smpr=0x0000_006x 2 3 4 5 6 7 8 1 t r t f 70% 30% vdde sck
package mechanical data PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 122 4 package mechanical data 4.1 144 lqfp
package mechanical data PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 123 figure 46. lqfp144 mechanical drawing (part 1 of 3)
package mechanical data PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 124 figure 47. lqfp144 mechanical drawing (part 2 of 3)
package mechanical data PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 125 figure 48. lqfp144 mechanical drawing (part 3 of 3)
package mechanical data PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 126 4.2 176 lqfp figure 49. lqfp176 mechanical drawing (part 1 of 3)
package mechanical data PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 127 figure 50. lqfp176 mechanical drawing (part 2 of 3)
package mechanical data PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 128 figure 51. lqfp176 mechanical drawing (part 3 of 3)
ordering information PXD10 microcontroller data sheet, rev. 1 freescale semiconductor 129 5 ordering information figure 52. PXD10 orderable part number description table 64. PXD10 orderable part number summary part number flash/sram package speed (mhz) mPXD1005vlq64 512 kb / 48 kb 144 lqfp (20 mm x 20 mm) 64 mPXD1010vlq64 1 mb / 48 kb 144 lqfp (20 mm x 20 mm) 64 mPXD1010vlu64 1 mb / 48 kb 176 lqfp (24 mm x 24 mm) 64 mpx 10 note: not all options are available on all devices. see ta bl e 6 4 for more information. d qualification status brand family class flash memory size temperature range v = ?40 c to 105 c operating frequency 64 = 64 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre-qualification (engineering samples) m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow 10 v temperature range lu package identifier 64 r operating frequency tape and reel indicator package identifier lq = 144 lqfp 120 = 120 mhz (ambient) lu = 176 lqfp family d = display graphics n = connectivity/network r = performance/real time control s=safety flash memory size 05 = 512 kb 10 = 1 mb
document number: PXD10 rev. 1 09/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2011. all rights reserved. 6 revision history table 65. document revision history revision date substantive changes 1 30 sep 2011 initial release.

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